1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend.rob.RobPtr 25import xiangshan.backend.rename.freelist._ 26 27class Rename(implicit p: Parameters) extends XSModule { 28 val io = IO(new Bundle() { 29 val redirect = Flipped(ValidIO(new Redirect)) 30 val robCommits = Flipped(new RobCommitIO) 31 // from decode 32 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 33 // to rename table 34 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 35 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 36 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 37 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 38 // to dispatch1 39 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 40 }) 41 42 // create free list and rat 43 val intFreeList = Module(new MEFreeList(MEFreeListSize)) 44 val intRefCounter = Module(new RefCounter(MEFreeListSize)) 45 val fpFreeList = Module(new StdFreeList(StdFreeListSize)) 46 47 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 48 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 49 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 50 } 51 def needDestRegCommit[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 52 if(fp) x.fpWen else x.rfWen 53 } 54 55 // connect [redirect + walk] ports for __float point__ & __integer__ free list 56 Seq((fpFreeList, true), (intFreeList, false)).foreach{ case (fl, isFp) => 57 fl.io.redirect := io.redirect.valid 58 fl.io.walk := io.robCommits.isWalk 59 // when isWalk, use stepBack to restore head pointer of free list 60 // (if ME enabled, stepBack of intFreeList should be useless thus optimized out) 61 fl.io.stepBack := PopCount(io.robCommits.valid.zip(io.robCommits.info).map{case (v, i) => v && needDestRegCommit(isFp, i)}) 62 } 63 // walk has higher priority than allocation and thus we don't use isWalk here 64 // only when both fp and int free list and dispatch1 has enough space can we do allocation 65 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready 66 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready 67 68 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 69 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 70 71 72 // speculatively assign the instruction with an robIdx 73 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter rob (from decode) 74 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 75 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 76 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 77 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 78 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 79 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 80 robIdxHead := robIdxHeadNext 81 82 /** 83 * Rename: allocate free physical register and update rename table 84 */ 85 val uops = Wire(Vec(RenameWidth, new MicroOp)) 86 uops.foreach( uop => { 87 uop.srcState(0) := DontCare 88 uop.srcState(1) := DontCare 89 uop.srcState(2) := DontCare 90 uop.robIdx := DontCare 91 uop.diffTestDebugLrScValid := DontCare 92 uop.debugInfo := DontCare 93 uop.lqIdx := DontCare 94 uop.sqIdx := DontCare 95 }) 96 97 val needFpDest = Wire(Vec(RenameWidth, Bool())) 98 val needIntDest = Wire(Vec(RenameWidth, Bool())) 99 val hasValid = Cat(io.in.map(_.valid)).orR 100 101 val isMove = io.in.map(_.bits.ctrl.isMove) 102 val intPsrc = Wire(Vec(RenameWidth, UInt())) 103 104 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 105 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 106 107 // uop calculation 108 for (i <- 0 until RenameWidth) { 109 uops(i).cf := io.in(i).bits.cf 110 uops(i).ctrl := io.in(i).bits.ctrl 111 112 val inValid = io.in(i).valid 113 114 // alloc a new phy reg 115 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 116 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 117 fpFreeList.io.allocateReq(i) := needFpDest(i) 118 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 119 120 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 121 io.in(i).ready := !hasValid || canOut 122 123 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(_.valid)) 124 125 val intPhySrcVec = io.intReadPorts(i).take(2) 126 val intOldPdest = io.intReadPorts(i).last 127 intPsrc(i) := intPhySrcVec(0) 128 val fpPhySrcVec = io.fpReadPorts(i).take(3) 129 val fpOldPdest = io.fpReadPorts(i).last 130 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 131 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 132 uops(i).psrc(2) := fpPhySrcVec(2) 133 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 134 uops(i).eliminatedMove := isMove(i) 135 136 // update pdest 137 uops(i).pdest := Mux(needIntDest(i), intFreeList.io.allocatePhyReg(i), // normal int inst 138 // normal fp inst 139 Mux(needFpDest(i), fpFreeList.io.allocatePhyReg(i), 140 /* default */0.U)) 141 142 // Assign performance counters 143 uops(i).debugInfo.renameTime := GTimer() 144 145 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 146 io.out(i).bits := uops(i) 147 when (io.out(i).bits.ctrl.fuType === FuType.fence) { 148 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0)) 149 } 150 151 // write speculative rename table 152 // we update rat later inside commit code 153 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 154 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 155 156 intRefCounter.io.allocate(i).valid := intSpecWen(i) 157 intRefCounter.io.allocate(i).bits := io.out(i).bits.pdest 158 } 159 160 /** 161 * How to set psrc: 162 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 163 * - default: psrc from RAT 164 * How to set pdest: 165 * - Mux(isMove, psrc, pdest_from_freelist). 166 * 167 * The critical path of rename lies here: 168 * When move elimination is enabled, we need to update the rat with psrc. 169 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 170 * 171 * If we expand these logic for pdest(N): 172 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 173 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 174 * Mux(bypass(N, N - 2), pdest(N - 2), 175 * ... 176 * Mux(bypass(N, 0), pdest(0), 177 * rat_out(N))...)), 178 * freelist_out(N)) 179 */ 180 // a simple functional model for now 181 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 182 val bypassCond = Wire(Vec(4, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 183 for (i <- 1 until RenameWidth) { 184 val fpCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 185 val intCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.reg) :+ needIntDest(i) 186 val target = io.in(i).bits.ctrl.lsrc :+ io.in(i).bits.ctrl.ldest 187 for ((((cond1, cond2), t), j) <- fpCond.zip(intCond).zip(target).zipWithIndex) { 188 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 189 val indexMatch = in.bits.ctrl.ldest === t 190 val writeMatch = cond2 && needIntDest(j) || cond1 && needFpDest(j) 191 indexMatch && writeMatch 192 } 193 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 194 } 195 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 196 (z, next) => Mux(next._2, next._1, z) 197 } 198 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 199 (z, next) => Mux(next._2, next._1, z) 200 } 201 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 202 (z, next) => Mux(next._2, next._1, z) 203 } 204 io.out(i).bits.old_pdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).old_pdest) { 205 (z, next) => Mux(next._2, next._1, z) 206 } 207 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 208 } 209 210 /** 211 * Instructions commit: update freelist and rename table 212 */ 213 for (i <- 0 until CommitWidth) { 214 215 Seq((io.intRenamePorts, false), (io.fpRenamePorts, true)) foreach { case (rat, fp) => 216 // is valid commit req and given instruction has destination register 217 val commitDestValid = io.robCommits.valid(i) && needDestRegCommit(fp, io.robCommits.info(i)) 218 XSDebug(p"isFp[${fp}]index[$i]-commitDestValid:$commitDestValid,isWalk:${io.robCommits.isWalk}\n") 219 220 /* 221 I. RAT Update 222 */ 223 224 // walk back write - restore spec state : ldest => old_pdest 225 if (fp && i < RenameWidth) { 226 // When redirect happens (mis-prediction), don't update the rename table 227 rat(i).wen := fpSpecWen(i) 228 rat(i).addr := uops(i).ctrl.ldest 229 rat(i).data := fpFreeList.io.allocatePhyReg(i) 230 } else if (!fp && i < RenameWidth) { 231 rat(i).wen := intSpecWen(i) 232 rat(i).addr := uops(i).ctrl.ldest 233 rat(i).data := io.out(i).bits.pdest 234 } 235 236 /* 237 II. Free List Update 238 */ 239 if (fp) { // Float Point free list 240 fpFreeList.io.freeReq(i) := commitDestValid && !io.robCommits.isWalk 241 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 242 } else { // Integer free list 243 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 244 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 245 } 246 } 247 intRefCounter.io.deallocate(i).valid := io.robCommits.valid(i) && needDestRegCommit(false, io.robCommits.info(i)) 248 intRefCounter.io.deallocate(i).bits := Mux(io.robCommits.isWalk, io.robCommits.info(i).pdest, io.robCommits.info(i).old_pdest) 249 } 250 251 /* 252 Debug and performance counters 253 */ 254 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 255 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.cf.pc)} in(${in.valid},${in.ready}) " + 256 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 257 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 258 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 259 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 260 p"old_pdest:${out.bits.old_pdest}\n" 261 ) 262 } 263 264 for((x,y) <- io.in.zip(io.out)){ 265 printRenameInfo(x, y) 266 } 267 268 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 269 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.valid.asUInt)}\n") 270 for (i <- 0 until CommitWidth) { 271 val info = io.robCommits.info(i) 272 XSDebug(io.robCommits.isWalk && io.robCommits.valid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 273 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} " + p"eliminatedMove:${info.eliminatedMove} " + 274 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 275 } 276 277 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 278 279 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 280 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 281 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 282 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 283 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 284 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 285 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 286 287 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire() && out.bits.ctrl.isMove))) 288 289 290 val intfl_perf = intFreeList.perfEvents.map(_._1).zip(intFreeList.perfinfo.perfEvents.perf_events) 291 val fpfl_perf = fpFreeList.perfEvents.map(_._1).zip(fpFreeList.perfinfo.perfEvents.perf_events) 292 val perf_list = Wire(new PerfEventsBundle(6)) 293 val perf_seq = Seq( 294 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 295 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 296 ("rename_stall_cycle_dispatch ", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk ), 297 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk ), 298 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk ), 299 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk ), 300 ) 301 for (((perf_out,(perf_name,perf)),i) <- perf_list.perf_events.zip(perf_seq).zipWithIndex) { 302 perf_out.incr_step := RegNext(perf) 303 } 304 305 val perfEvents_list = perf_list.perf_events ++ 306 intFreeList.asInstanceOf[freelist.MEFreeList].perfinfo.perfEvents.perf_events ++ 307 fpFreeList.perfinfo.perfEvents.perf_events 308 309 val perfEvents = perf_seq ++ intfl_perf ++ fpfl_perf 310 val perfinfo = IO(new Bundle(){ 311 val perfEvents = Output(new PerfEventsBundle(perfEvents_list.length)) 312 }) 313 perfinfo.perfEvents.perf_events := perfEvents_list 314} 315