1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 26import xiangshan.backend.rob.RobPtr 27import xiangshan.backend.rename.freelist._ 28import xiangshan.mem.mdp._ 29 30class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 31 val io = IO(new Bundle() { 32 val redirect = Flipped(ValidIO(new Redirect)) 33 val robCommits = Input(new RobCommitIO) 34 // from decode 35 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 36 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 37 // ssit read result 38 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 39 // waittable read result 40 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 41 // to rename table 42 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 43 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 44 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 45 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 46 // to dispatch1 47 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 48 // debug arch ports 49 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 50 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 51 }) 52 53 // create free list and rat 54 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 55 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 56 val fpFreeList = Module(new StdFreeList(NRPhyRegs - 32)) 57 58 intRefCounter.io.commit <> io.robCommits 59 intRefCounter.io.redirect := io.redirect.valid 60 intRefCounter.io.debug_int_rat <> io.debug_int_rat 61 intFreeList.io.commit <> io.robCommits 62 intFreeList.io.debug_rat <> io.debug_int_rat 63 fpFreeList.io.commit <> io.robCommits 64 fpFreeList.io.debug_rat <> io.debug_fp_rat 65 66 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 67 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 68 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 69 } 70 def needDestRegCommit[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 71 if(fp) x.fpWen else x.rfWen 72 } 73 def needDestRegWalk[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 74 if(fp) x.fpWen else x.rfWen && x.ldest =/= 0.U 75 } 76 77 // connect [redirect + walk] ports for __float point__ & __integer__ free list 78 Seq((fpFreeList, true), (intFreeList, false)).foreach{ case (fl, isFp) => 79 fl.io.redirect := io.redirect.valid 80 fl.io.walk := io.robCommits.isWalk 81 } 82 // only when both fp and int free list and dispatch1 has enough space can we do allocation 83 // when isWalk, freelist can definitely allocate 84 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 85 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 86 87 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 88 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 89 90 91 // speculatively assign the instruction with an robIdx 92 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter rob (from decode) 93 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 94 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 95 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 96 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 97 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 98 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 99 robIdxHead := robIdxHeadNext 100 101 /** 102 * Rename: allocate free physical register and update rename table 103 */ 104 val uops = Wire(Vec(RenameWidth, new MicroOp)) 105 uops.foreach( uop => { 106 uop.srcState(0) := DontCare 107 uop.srcState(1) := DontCare 108 uop.srcState(2) := DontCare 109 uop.robIdx := DontCare 110 uop.debugInfo := DontCare 111 uop.lqIdx := DontCare 112 uop.sqIdx := DontCare 113 }) 114 115 require(RenameWidth >= CommitWidth) 116 117 val needFpDest = Wire(Vec(RenameWidth, Bool())) 118 val needIntDest = Wire(Vec(RenameWidth, Bool())) 119 val hasValid = Cat(io.in.map(_.valid)).orR 120 121 val isMove = io.in.map(_.bits.ctrl.isMove) 122 123 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 124 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 125 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 126 127 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 128 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 129 130 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 131 132 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 133 134 // uop calculation 135 for (i <- 0 until RenameWidth) { 136 uops(i).cf := io.in(i).bits.cf 137 uops(i).ctrl := io.in(i).bits.ctrl 138 139 // update cf according to ssit result 140 uops(i).cf.storeSetHit := io.ssit(i).valid 141 uops(i).cf.loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 142 uops(i).cf.ssid := io.ssit(i).ssid 143 144 // update cf according to waittable result 145 uops(i).cf.loadWaitBit := io.waittable(i) 146 147 // alloc a new phy reg 148 needFpDest(i) := io.in(i).valid && needDestReg(fp = true, io.in(i).bits) 149 needIntDest(i) := io.in(i).valid && needDestReg(fp = false, io.in(i).bits) 150 if (i < CommitWidth) { 151 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(fp = true, io.robCommits.info(i)) 152 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(fp = false, io.robCommits.info(i)) 153 walkIsMove(i) := io.robCommits.info(i).isMove 154 } 155 fpFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedFpDest(i), needFpDest(i)) 156 intFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedIntDest(i) && !walkIsMove(i), needIntDest(i) && !isMove(i)) 157 158 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 159 io.in(i).ready := !hasValid || canOut 160 161 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(_.valid)) 162 163 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, io.intReadPorts(i)(0), io.fpReadPorts(i)(0)) 164 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, io.intReadPorts(i)(1), io.fpReadPorts(i)(1)) 165 // int psrc2 should be bypassed from next instruction if it is fused 166 if (i < RenameWidth - 1) { 167 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 168 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 169 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 170 uops(i).psrc(1) := 0.U 171 } 172 } 173 uops(i).psrc(2) := io.fpReadPorts(i)(2) 174 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, io.intReadPorts(i).last, io.fpReadPorts(i).last) 175 uops(i).eliminatedMove := isMove(i) 176 177 // update pdest 178 uops(i).pdest := Mux(needIntDest(i), intFreeList.io.allocatePhyReg(i), // normal int inst 179 // normal fp inst 180 Mux(needFpDest(i), fpFreeList.io.allocatePhyReg(i), 181 /* default */0.U)) 182 183 // Assign performance counters 184 uops(i).debugInfo.renameTime := GTimer() 185 186 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 187 io.out(i).bits := uops(i) 188 // dirty code for fence. The lsrc is passed by imm. 189 when (io.out(i).bits.ctrl.fuType === FuType.fence) { 190 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0)) 191 } 192 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 193 when (io.in(i).bits.ctrl.isSoftPrefetch) { 194 io.out(i).bits.ctrl.fuType := FuType.ldu 195 io.out(i).bits.ctrl.fuOpType := Mux(io.in(i).bits.ctrl.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 196 io.out(i).bits.ctrl.selImm := SelImm.IMM_S 197 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.imm(io.in(i).bits.ctrl.imm.getWidth - 1, 5), 0.U(5.W)) 198 } 199 200 // write speculative rename table 201 // we update rat later inside commit code 202 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 203 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 204 205 if (i < CommitWidth) { 206 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 207 walkPdest(i) := io.robCommits.info(i).pdest 208 } else { 209 walkPdest(i) := io.out(i).bits.pdest 210 } 211 212 intRefCounter.io.allocate(i).valid := Mux(io.robCommits.isWalk, walkIntSpecWen(i), intSpecWen(i)) 213 intRefCounter.io.allocate(i).bits := Mux(io.robCommits.isWalk, walkPdest(i), io.out(i).bits.pdest) 214 } 215 216 /** 217 * How to set psrc: 218 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 219 * - default: psrc from RAT 220 * How to set pdest: 221 * - Mux(isMove, psrc, pdest_from_freelist). 222 * 223 * The critical path of rename lies here: 224 * When move elimination is enabled, we need to update the rat with psrc. 225 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 226 * 227 * If we expand these logic for pdest(N): 228 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 229 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 230 * Mux(bypass(N, N - 2), pdest(N - 2), 231 * ... 232 * Mux(bypass(N, 0), pdest(0), 233 * rat_out(N))...)), 234 * freelist_out(N)) 235 */ 236 // a simple functional model for now 237 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 238 val bypassCond = Wire(Vec(4, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 239 for (i <- 1 until RenameWidth) { 240 val fpCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 241 val intCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.reg) :+ needIntDest(i) 242 val target = io.in(i).bits.ctrl.lsrc :+ io.in(i).bits.ctrl.ldest 243 for ((((cond1, cond2), t), j) <- fpCond.zip(intCond).zip(target).zipWithIndex) { 244 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 245 val indexMatch = in.bits.ctrl.ldest === t 246 val writeMatch = cond2 && needIntDest(j) || cond1 && needFpDest(j) 247 indexMatch && writeMatch 248 } 249 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 250 } 251 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 252 (z, next) => Mux(next._2, next._1, z) 253 } 254 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 255 (z, next) => Mux(next._2, next._1, z) 256 } 257 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 258 (z, next) => Mux(next._2, next._1, z) 259 } 260 io.out(i).bits.old_pdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).old_pdest) { 261 (z, next) => Mux(next._2, next._1, z) 262 } 263 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 264 265 // For fused-lui-load, load.src(0) is replaced by the imm. 266 val last_is_lui = io.in(i - 1).bits.ctrl.selImm === SelImm.IMM_U && io.in(i - 1).bits.ctrl.srcType(0) =/= SrcType.pc 267 val this_is_load = io.in(i).bits.ctrl.fuType === FuType.ldu 268 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 269 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 270 when (fused_lui_load) { 271 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 272 val lui_imm = io.in(i - 1).bits.ctrl.imm 273 val ld_imm = io.in(i).bits.ctrl.imm 274 io.out(i).bits.ctrl.srcType(0) := SrcType.imm 275 io.out(i).bits.ctrl.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 276 val psrcWidth = uops(i).psrc.head.getWidth 277 val lui_imm_in_imm = uops(i).ctrl.imm.getWidth - Imm_I().len 278 val left_lui_imm = Imm_U().len - lui_imm_in_imm 279 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 280 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 281 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 282 } 283 284 } 285 286 /** 287 * Instructions commit: update freelist and rename table 288 */ 289 for (i <- 0 until CommitWidth) { 290 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 291 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 292 293 Seq((io.intRenamePorts, false), (io.fpRenamePorts, true)) foreach { case (rat, fp) => 294 /* 295 I. RAT Update 296 */ 297 298 // walk back write - restore spec state : ldest => old_pdest 299 if (fp && i < RenameWidth) { 300 // When redirect happens (mis-prediction), don't update the rename table 301 rat(i).wen := fpSpecWen(i) 302 rat(i).addr := uops(i).ctrl.ldest 303 rat(i).data := fpFreeList.io.allocatePhyReg(i) 304 } else if (!fp && i < RenameWidth) { 305 rat(i).wen := intSpecWen(i) 306 rat(i).addr := uops(i).ctrl.ldest 307 rat(i).data := io.out(i).bits.pdest 308 } 309 310 /* 311 II. Free List Update 312 */ 313 if (fp) { // Float Point free list 314 fpFreeList.io.freeReq(i) := commitValid && needDestRegCommit(fp, io.robCommits.info(i)) 315 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 316 } else { // Integer free list 317 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 318 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 319 } 320 } 321 intRefCounter.io.deallocate(i).valid := commitValid && needDestRegCommit(false, io.robCommits.info(i)) && !io.robCommits.isWalk 322 intRefCounter.io.deallocate(i).bits := io.robCommits.info(i).old_pdest 323 } 324 325 when(io.robCommits.isWalk) { 326 (intFreeList.io.allocateReq zip intFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 327 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 328 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 329 } 330 } 331 (fpFreeList.io.allocateReq zip fpFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 332 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 333 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 334 } 335 } 336 } 337 338 /* 339 Debug and performance counters 340 */ 341 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 342 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.cf.pc)} in(${in.valid},${in.ready}) " + 343 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 344 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 345 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 346 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 347 p"old_pdest:${out.bits.old_pdest}\n" 348 ) 349 } 350 351 for((x,y) <- io.in.zip(io.out)){ 352 printRenameInfo(x, y) 353 } 354 355 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 356 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 357 for (i <- 0 until CommitWidth) { 358 val info = io.robCommits.info(i) 359 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 360 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} " + 361 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 362 } 363 364 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 365 366 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 367 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 368 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 369 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 370 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 371 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 372 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 373 XSPerfAccumulate("recovery_bubbles", PopCount(io.in.map(_.valid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk))) 374 375 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.ctrl.isMove))) 376 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.ctrl.fuType === FuType.ldu && o.bits.ctrl.srcType(0) === SrcType.imm) 377 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 378 379 380 val renamePerf = Seq( 381 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 382 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 383 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 384 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 385 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 386 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 387 ) 388 val intFlPerf = intFreeList.getPerfEvents 389 val fpFlPerf = fpFreeList.getPerfEvents 390 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 391 generatePerfEvent() 392} 393