1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.{RobEnqIO, RobPtr} 30import xiangshan.mem.mdp._ 31 32class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 33 34 // params alias 35 private val numRegSrc = backendParams.numRegSrc 36 private val numVecRegSrc = backendParams.numVecRegSrc 37 private val numVecRatPorts = numVecRegSrc 38 39 println(s"[Rename] numRegSrc: $numRegSrc") 40 41 val io = IO(new Bundle() { 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val rabCommits = Input(new RabCommitIO) 44 // from decode 45 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 46 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 47 // ssit read result 48 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 49 // waittable read result 50 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 51 // to rename table 52 val intReadPorts = Vec(RenameWidth, Vec(2, Input(UInt(PhyRegIdxWidth.W)))) 53 val fpReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 54 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 55 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 56 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 57 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 58 // from rename table 59 val int_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 60 val fp_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 61 val vec_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 62 val int_need_free = Vec(RabCommitWidth, Input(Bool())) 63 // to dispatch1 64 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 65 // for snapshots 66 val snpt = Input(new SnapshotPort) 67 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 68 val snptIsFull= Input(Bool()) 69 // debug arch ports 70 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 71 val debug_vconfig_rat = if (backendParams.debugEn) Some(Input(UInt(PhyRegIdxWidth.W))) else None 72 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 73 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 74 // perf only 75 val stallReason = new Bundle { 76 val in = Flipped(new StallReasonIO(RenameWidth)) 77 val out = new StallReasonIO(RenameWidth) 78 } 79 }) 80 81 val compressUnit = Module(new CompressUnit()) 82 // create free list and rat 83 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 84 val fpFreeList = Module(new StdFreeList(FpPhyRegs - FpLogicRegs, FpLogicRegs, Reg_F)) 85 val vecFreeList = Module(new StdFreeList(VfPhyRegs - VecLogicRegs, VecLogicRegs, Reg_V)) 86 87 intFreeList.io.commit <> io.rabCommits 88 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 89 fpFreeList.io.commit <> io.rabCommits 90 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 91 vecFreeList.io.commit <> io.rabCommits 92 vecFreeList.io.debug_rat.foreach(_ <> io.debug_vec_rat.get) 93 94 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 95 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 96 case Reg_I => x.rfWen && x.ldest =/= 0.U 97 case Reg_F => x.fpWen 98 case Reg_V => x.vecWen 99 } 100 def needDestRegCommit[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 101 reg_t match { 102 case Reg_I => x.rfWen 103 case Reg_F => x.fpWen 104 case Reg_V => x.vecWen 105 } 106 } 107 def needDestRegWalk[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 108 reg_t match { 109 case Reg_I => x.rfWen && x.ldest =/= 0.U 110 case Reg_F => x.fpWen 111 case Reg_V => x.vecWen 112 } 113 } 114 115 // connect [redirect + walk] ports for fp & vec & int free list 116 Seq(fpFreeList, vecFreeList, intFreeList).foreach { case fl => 117 fl.io.redirect := io.redirect.valid 118 fl.io.walk := io.rabCommits.isWalk 119 } 120 // only when all free list and dispatch1 has enough space can we do allocation 121 // when isWalk, freelist can definitely allocate 122 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && io.out(0).ready || io.rabCommits.isWalk 123 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && vecFreeList.io.canAllocate && io.out(0).ready || io.rabCommits.isWalk 124 vecFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && io.out(0).ready || io.rabCommits.isWalk 125 126 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ vec free list ready ++ not walk 127 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && !io.rabCommits.isWalk 128 129 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 130 sink.valid := source.valid 131 sink.bits := source.bits 132 } 133 val needRobFlags = compressUnit.io.out.needRobFlags 134 val instrSizesVec = compressUnit.io.out.instrSizes 135 val compressMasksVec = compressUnit.io.out.masks 136 137 // speculatively assign the instruction with an robIdx 138 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 139 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 140 val lastCycleMisprediction = GatedValidRegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 141 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 142 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 143 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 144 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 145 robIdxHead := robIdxHeadNext 146 147 /** 148 * Rename: allocate free physical register and update rename table 149 */ 150 val uops = Wire(Vec(RenameWidth, new DynInst)) 151 uops.foreach( uop => { 152 uop.srcState := DontCare 153 uop.debugInfo := DontCare 154 uop.lqIdx := DontCare 155 uop.sqIdx := DontCare 156 uop.waitForRobIdx := DontCare 157 uop.singleStep := DontCare 158 uop.snapshot := DontCare 159 uop.srcLoadDependency := DontCare 160 }) 161 162 val needVecDest = Wire(Vec(RenameWidth, Bool())) 163 val needFpDest = Wire(Vec(RenameWidth, Bool())) 164 val needIntDest = Wire(Vec(RenameWidth, Bool())) 165 val hasValid = Cat(io.in.map(_.valid)).orR 166 private val inHeadValid = io.in.head.valid 167 168 val isMove = Wire(Vec(RenameWidth, Bool())) 169 isMove zip io.in.map(_.bits) foreach { 170 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 171 } 172 173 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 174 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 175 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 176 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 177 178 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 179 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 180 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 181 182 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 183 184 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 185 186 // uop calculation 187 for (i <- 0 until RenameWidth) { 188 (uops(i): Data).waiveAll :<= (io.in(i).bits: Data).waiveAll 189 190 // update cf according to ssit result 191 uops(i).storeSetHit := io.ssit(i).valid 192 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 193 uops(i).ssid := io.ssit(i).ssid 194 195 // update cf according to waittable result 196 uops(i).loadWaitBit := io.waittable(i) 197 198 uops(i).replayInst := false.B // set by IQ or MemQ 199 // alloc a new phy reg 200 needVecDest(i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 201 needFpDest(i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 202 needIntDest(i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 203 if (i < RabCommitWidth) { 204 walkNeedIntDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_I, io.rabCommits.info(i)) 205 walkNeedFpDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_F, io.rabCommits.info(i)) 206 walkNeedVecDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V, io.rabCommits.info(i)) 207 walkIsMove(i) := io.rabCommits.info(i).isMove 208 } 209 fpFreeList.io.allocateReq(i) := needFpDest(i) 210 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) 211 vecFreeList.io.allocateReq(i) := needVecDest(i) 212 vecFreeList.io.walkReq(i) := walkNeedVecDest(i) 213 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 214 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 215 216 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 217 io.in(i).ready := !hasValid || canOut 218 219 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 220 uops(i).instrSize := instrSizesVec(i) 221 when(isMove(i)) { 222 uops(i).numUops := 0.U 223 uops(i).numWB := 0.U 224 } 225 if (i > 0) { 226 when(!needRobFlags(i - 1)) { 227 uops(i).firstUop := false.B 228 uops(i).ftqPtr := uops(i - 1).ftqPtr 229 uops(i).ftqOffset := uops(i - 1).ftqOffset 230 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 231 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 232 } 233 } 234 when(!needRobFlags(i)) { 235 uops(i).lastUop := false.B 236 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 237 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 238 } 239 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 240 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 241 // vector instructions' uopSplitType cannot be UopSplitType.SCA_SIM 242 uops(i).dirtyVs := (compressMasksVec(i) & Cat(io.in.map(_.bits.uopSplitType =/= UopSplitType.SCA_SIM).reverse)).orR 243 244 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 245 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 246 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 247 uops(i).psrc(3) := io.vecReadPorts(i)(3) 248 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 249 250 // int psrc2 should be bypassed from next instruction if it is fused 251 if (i < RenameWidth - 1) { 252 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 253 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 254 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 255 uops(i).psrc(1) := 0.U 256 } 257 } 258 uops(i).eliminatedMove := isMove(i) 259 260 // update pdest 261 uops(i).pdest := MuxCase(0.U, Seq( 262 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 263 needFpDest(i) -> fpFreeList.io.allocatePhyReg(i), 264 needVecDest(i) -> vecFreeList.io.allocatePhyReg(i), 265 )) 266 267 // Assign performance counters 268 uops(i).debugInfo.renameTime := GTimer() 269 270 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && !io.rabCommits.isWalk 271 io.out(i).bits := uops(i) 272 // Todo: move these shit in decode stage 273 // dirty code for fence. The lsrc is passed by imm. 274 when (io.out(i).bits.fuType === FuType.fence.U) { 275 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 276 } 277 278 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 279// when (io.in(i).bits.isSoftPrefetch) { 280// io.out(i).bits.fuType := FuType.ldu.U 281// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 282// io.out(i).bits.selImm := SelImm.IMM_S 283// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 284// } 285 286 // dirty code for lui+addi(w) fusion 287 if (i < RenameWidth - 1) { 288 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 289 when (fused_lui32) { 290 val lui_imm = io.in(i).bits.imm(19, 0) 291 val add_imm = io.in(i + 1).bits.imm(11, 0) 292 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + add_imm.getWidth) 293 io.out(i).bits.imm := Cat(lui_imm, add_imm) 294 } 295 } 296 297 // write speculative rename table 298 // we update rat later inside commit code 299 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 300 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 301 vecSpecWen(i) := needVecDest(i) && vecFreeList.io.canAllocate && vecFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 302 303 304 if (i < RabCommitWidth) { 305 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 306 walkPdest(i) := io.rabCommits.info(i).pdest 307 } else { 308 walkPdest(i) := io.out(i).bits.pdest 309 } 310 } 311 312 /** 313 * How to set psrc: 314 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 315 * - default: psrc from RAT 316 * How to set pdest: 317 * - Mux(isMove, psrc, pdest_from_freelist). 318 * 319 * The critical path of rename lies here: 320 * When move elimination is enabled, we need to update the rat with psrc. 321 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 322 * 323 * If we expand these logic for pdest(N): 324 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 325 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 326 * Mux(bypass(N, N - 2), pdest(N - 2), 327 * ... 328 * Mux(bypass(N, 0), pdest(0), 329 * rat_out(N))...)), 330 * freelist_out(N)) 331 */ 332 // a simple functional model for now 333 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 334 335 // psrc(n) + pdest(1) 336 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 337 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 338 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 339 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 340 for (i <- 1 until RenameWidth) { 341 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 342 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 343 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 344 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 345 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 346 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 347 val indexMatch = in.bits.ldest === t 348 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 349 indexMatch && writeMatch 350 } 351 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 352 } 353 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 354 (z, next) => Mux(next._2, next._1, z) 355 } 356 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 357 (z, next) => Mux(next._2, next._1, z) 358 } 359 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 360 (z, next) => Mux(next._2, next._1, z) 361 } 362 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 363 (z, next) => Mux(next._2, next._1, z) 364 } 365 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 366 (z, next) => Mux(next._2, next._1, z) 367 } 368 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 369 370 // Todo: better implementation for fields reuse 371 // For fused-lui-load, load.src(0) is replaced by the imm. 372 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 373 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 374 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 375 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 376 when (fused_lui_load) { 377 // The first LOAD operand (base address) is replaced by LUI-imm and stored in imm 378 val lui_imm = io.in(i - 1).bits.imm(ImmUnion.U.len - 1, 0) 379 val ld_imm = io.in(i).bits.imm(ImmUnion.I.len - 1, 0) 380 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + ld_imm.getWidth) 381 io.out(i).bits.srcType(0) := SrcType.imm 382 io.out(i).bits.imm := Cat(lui_imm, ld_imm) 383 } 384 385 } 386 387 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 388 val lastCycleCreateSnpt = RegInit(false.B) 389 lastCycleCreateSnpt := genSnapshot && !io.snptIsFull 390 val sameSnptDistance = (RobCommitWidth * 4).U 391 // notInSameSnpt: 1.robidxHead - snapLastEnq >= sameSnptDistance 2.no snap 392 val notInSameSnpt = GatedValidRegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= sameSnptDistance || !io.snptLastEnq.valid) 393 val allowSnpt = if (EnableRenameSnapshot) notInSameSnpt && !lastCycleCreateSnpt && io.in.head.bits.firstUop else false.B 394 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 395 if(backendParams.debugEn){ 396 dontTouch(robIdxHeadNext) 397 dontTouch(notInSameSnpt) 398 dontTouch(genSnapshot) 399 } 400 intFreeList.io.snpt := io.snpt 401 fpFreeList.io.snpt := io.snpt 402 vecFreeList.io.snpt := io.snpt 403 intFreeList.io.snpt.snptEnq := genSnapshot 404 fpFreeList.io.snpt.snptEnq := genSnapshot 405 vecFreeList.io.snpt.snptEnq := genSnapshot 406 407 /** 408 * Instructions commit: update freelist and rename table 409 */ 410 for (i <- 0 until RabCommitWidth) { 411 val commitValid = io.rabCommits.isCommit && io.rabCommits.commitValid(i) 412 val walkValid = io.rabCommits.isWalk && io.rabCommits.walkValid(i) 413 414 // I. RAT Update 415 // When redirect happens (mis-prediction), don't update the rename table 416 io.intRenamePorts(i).wen := intSpecWen(i) 417 io.intRenamePorts(i).addr := uops(i).ldest 418 io.intRenamePorts(i).data := io.out(i).bits.pdest 419 420 io.fpRenamePorts(i).wen := fpSpecWen(i) 421 io.fpRenamePorts(i).addr := uops(i).ldest 422 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 423 424 io.vecRenamePorts(i).wen := vecSpecWen(i) 425 io.vecRenamePorts(i).addr := uops(i).ldest 426 io.vecRenamePorts(i).data := vecFreeList.io.allocatePhyReg(i) 427 428 // II. Free List Update 429 intFreeList.io.freeReq(i) := io.int_need_free(i) 430 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 431 fpFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_F, io.rabCommits.info(i))) 432 fpFreeList.io.freePhyReg(i) := io.fp_old_pdest(i) 433 vecFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V, io.rabCommits.info(i))) 434 vecFreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 435 } 436 437 /* 438 Debug and performance counters 439 */ 440 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 441 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 442 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 443 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 444 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 445 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 446 ) 447 } 448 449 for ((x,y) <- io.in.zip(io.out)) { 450 printRenameInfo(x, y) 451 } 452 453 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 454 // bad speculation 455 val recStall = io.redirect.valid || io.rabCommits.isWalk 456 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.rabCommits.isWalk && debugRedirect.debugIsCtrl) 457 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.rabCommits.isWalk && debugRedirect.debugIsMemVio) 458 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 459 XSPerfAccumulate("recovery_stall", recStall) 460 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 461 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 462 XSPerfAccumulate("other_recovery_stall", otherRecStall) 463 // freelist stall 464 val notRecStall = !io.out.head.valid && !recStall 465 val intFlStall = notRecStall && inHeadValid && !intFreeList.io.canAllocate 466 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && !fpFreeList.io.canAllocate 467 val vecFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !vecFreeList.io.canAllocate 468 // other stall 469 val otherStall = notRecStall && !intFlStall && !fpFlStall && !vecFlStall 470 471 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 472 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 473 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 474 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 475 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 476 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 477 intFlStall -> TopDownCounters.IntFlStall.id.U, 478 fpFlStall -> TopDownCounters.FpFlStall.id.U, 479 vecFlStall -> TopDownCounters.VecFlStall.id.U, 480 ) 481 )) 482 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 483 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 484 } 485 486 XSDebug(io.rabCommits.isWalk, p"Walk Recovery Enabled\n") 487 XSDebug(io.rabCommits.isWalk, p"validVec:${Binary(io.rabCommits.walkValid.asUInt)}\n") 488 for (i <- 0 until RabCommitWidth) { 489 val info = io.rabCommits.info(i) 490 XSDebug(io.rabCommits.isWalk && io.rabCommits.walkValid(i), p"[#$i walk info] " + 491 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}") 492 } 493 494 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 495 496 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 497 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 498 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 499 XSPerfAccumulate("wait_cycle", !io.in.head.valid && io.out.head.ready) 500 501 // These stall reasons could overlap each other, but we configure the priority as fellows. 502 // walk stall > dispatch stall > int freelist stall > fp freelist stall 503 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 504 private val stallForWalk = inHeadValid && io.rabCommits.isWalk 505 private val stallForDispatch = inHeadValid && !io.rabCommits.isWalk && !io.out(0).ready 506 private val stallForIntFL = inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && !intFreeList.io.canAllocate 507 private val stallForFpFL = inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && !fpFreeList.io.canAllocate 508 private val stallForVecFL = inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !vecFreeList.io.canAllocate 509 XSPerfAccumulate("stall_cycle", inHeadStall) 510 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 511 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 512 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 513 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 514 XSPerfAccumulate("stall_cycle_vec", stallForVecFL) 515 516 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 517 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 518 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 519 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 520 521 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 522 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 523 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 524 525 val renamePerf = Seq( 526 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 527 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 528 ("rename_stall ", inHeadStall), 529 ("rename_stall_cycle_walk ", inHeadValid && io.rabCommits.isWalk), 530 ("rename_stall_cycle_dispatch", inHeadValid && !io.rabCommits.isWalk && !io.out(0).ready), 531 ("rename_stall_cycle_int ", inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && !intFreeList.io.canAllocate), 532 ("rename_stall_cycle_fp ", inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 533 ("rename_stall_cycle_vec ", inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !vecFreeList.io.canAllocate), 534 ) 535 val intFlPerf = intFreeList.getPerfEvents 536 val fpFlPerf = fpFreeList.getPerfEvents 537 val vecFlPerf = vecFreeList.getPerfEvents 538 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf ++ vecFlPerf 539 generatePerfEvent() 540} 541