1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.XSInfo 7 8class Rename extends XSModule { 9 val io = IO(new Bundle() { 10 val redirect = Flipped(ValidIO(new Redirect)) 11 val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) 12 // from decode buffer 13 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 14 // to dispatch1 15 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 16 }) 17 18 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 19 XSInfo( 20 in.valid && in.ready, 21 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 22 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 23 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 24 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 25 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 26 p"old_pdest:${out.bits.old_pdest} " + 27 p"out v:${out.valid} r:${out.ready}\n" 28 ) 29 } 30 31 for((x,y) <- io.in.zip(io.out)){ 32 printRenameInfo(x, y) 33 } 34 35 val fpFreeList, intFreeList = Module(new FreeList).io 36 val fpRat = Module(new RenameTable(float = true)).io 37 val intRat = Module(new RenameTable(float = false)).io 38 39 fpFreeList.redirect := io.redirect 40 intFreeList.redirect := io.redirect 41 42 val flush = io.redirect.valid && (io.redirect.bits.isException || io.redirect.bits.isFlushPipe) // TODO: need check by JiaWei 43 fpRat.flush := flush 44 intRat.flush := flush 45 46 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 47 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 48 } 49 50 val uops = Wire(Vec(RenameWidth, new MicroOp)) 51 52 uops.foreach( uop => { 53// uop.brMask := DontCare 54// uop.brTag := DontCare 55 uop.src1State := DontCare 56 uop.src2State := DontCare 57 uop.src3State := DontCare 58 uop.roqIdx := DontCare 59 uop.diffTestDebugLrScValid := DontCare 60 uop.lqIdx := DontCare 61 uop.sqIdx := DontCare 62 }) 63 64 var lastReady = WireInit(io.out(0).ready) 65 // debug assert 66 val outRdy = Cat(io.out.map(_.ready)) 67 assert(outRdy===0.U || outRdy.andR()) 68 for(i <- 0 until RenameWidth) { 69 uops(i).cf := io.in(i).bits.cf 70 uops(i).ctrl := io.in(i).bits.ctrl 71 uops(i).brTag := io.in(i).bits.brTag 72 73 val inValid = io.in(i).valid 74 75 // alloc a new phy reg 76 val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits) 77 val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits) 78 fpFreeList.allocReqs(i) := needFpDest && lastReady 79 intFreeList.allocReqs(i) := needIntDest && lastReady 80 val fpCanAlloc = fpFreeList.canAlloc(i) 81 val intCanAlloc = intFreeList.canAlloc(i) 82 val this_can_alloc = Mux( 83 needIntDest, 84 intCanAlloc, 85 Mux( 86 needFpDest, 87 fpCanAlloc, 88 true.B 89 ) 90 ) 91 io.in(i).ready := lastReady && this_can_alloc 92 93 // do checkpoints when a branch inst come 94 for(fl <- Seq(fpFreeList, intFreeList)){ 95 fl.cpReqs(i).valid := inValid 96 fl.cpReqs(i).bits := io.in(i).bits.brTag 97 } 98 99 lastReady = io.in(i).ready 100 101 uops(i).pdest := Mux(needIntDest, 102 intFreeList.pdests(i), 103 Mux( 104 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 105 0.U, fpFreeList.pdests(i) 106 ) 107 ) 108 109 io.out(i).valid := io.in(i).fire() 110 io.out(i).bits := uops(i) 111 112 // write rename table 113 def writeRat(fp: Boolean) = { 114 val rat = if(fp) fpRat else intRat 115 val freeList = if(fp) fpFreeList else intFreeList 116 // speculative inst write 117 val specWen = freeList.allocReqs(i) && freeList.canAlloc(i) 118 // walk back write 119 val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop) 120 val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk 121 122 rat.specWritePorts(i).wen := specWen || walkWen 123 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest) 124 rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest) 125 126 XSInfo(walkWen, 127 {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" + 128 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 129 ) 130 131 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk 132 rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest 133 rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest 134 135 XSInfo(rat.archWritePorts(i).wen, 136 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 137 p" pdest:${rat.archWritePorts(i).wdata}\n" 138 ) 139 140 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 141 freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest 142 143 } 144 145 writeRat(fp = false) 146 writeRat(fp = true) 147 148 // read rename table 149 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 150 val rat = if(fp) fpRat else intRat 151 val srcCnt = lsrcList.size 152 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 153 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 154 for(k <- 0 until srcCnt+1){ 155 val rportIdx = i * (srcCnt+1) + k 156 if(k != srcCnt){ 157 rat.readPorts(rportIdx).addr := lsrcList(k) 158 psrcVec(k) := rat.readPorts(rportIdx).rdata 159 } else { 160 rat.readPorts(rportIdx).addr := ldest 161 old_pdest := rat.readPorts(rportIdx).rdata 162 } 163 } 164 (psrcVec, old_pdest) 165 } 166 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 167 val ldest = uops(i).ctrl.ldest 168 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 169 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 170 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 171 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 172 uops(i).psrc3 := fpPhySrcVec(2) 173 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 174 } 175 176 177 178} 179