1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.{RobEnqIO, RobPtr} 30import xiangshan.mem.mdp._ 31import xiangshan.ExceptionNO._ 32import xiangshan.backend.fu.FuType._ 33import xiangshan.mem.{EewLog2, GenUSWholeEmul} 34import xiangshan.mem.GenRealFlowNum 35 36class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 37 38 // params alias 39 private val numRegSrc = backendParams.numRegSrc 40 private val numVecRegSrc = backendParams.numVecRegSrc 41 private val numVecRatPorts = numVecRegSrc 42 43 println(s"[Rename] numRegSrc: $numRegSrc") 44 45 val io = IO(new Bundle() { 46 val redirect = Flipped(ValidIO(new Redirect)) 47 val rabCommits = Input(new RabCommitIO) 48 // from decode 49 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 50 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 51 // ssit read result 52 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 53 // waittable read result 54 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 55 // to rename table 56 val intReadPorts = Vec(RenameWidth, Vec(2, Input(UInt(PhyRegIdxWidth.W)))) 57 val fpReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 58 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 59 val v0ReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 60 val vlReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 61 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(IntLogicRegs)))) 62 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(FpLogicRegs)))) 63 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(VecLogicRegs)))) 64 val v0RenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(V0LogicRegs)))) 65 val vlRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(VlLogicRegs)))) 66 // from rename table 67 val int_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 68 val fp_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 69 val vec_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 70 val v0_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 71 val vl_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 72 val int_need_free = Vec(RabCommitWidth, Input(Bool())) 73 // to dispatch1 74 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 75 // for snapshots 76 val snpt = Input(new SnapshotPort) 77 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 78 val snptIsFull= Input(Bool()) 79 // debug arch ports 80 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 81 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 82 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Input(UInt(PhyRegIdxWidth.W)))) else None 83 val debug_v0_rat = if (backendParams.debugEn) Some(Vec(1, Input(UInt(PhyRegIdxWidth.W)))) else None 84 val debug_vl_rat = if (backendParams.debugEn) Some(Vec(1, Input(UInt(PhyRegIdxWidth.W)))) else None 85 // perf only 86 val stallReason = new Bundle { 87 val in = Flipped(new StallReasonIO(RenameWidth)) 88 val out = new StallReasonIO(RenameWidth) 89 } 90 }) 91 92 // io alias 93 private val dispatchCanAcc = io.out.head.ready 94 95 val compressUnit = Module(new CompressUnit()) 96 // create free list and rat 97 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 98 val fpFreeList = Module(new StdFreeList(FpPhyRegs - FpLogicRegs, FpLogicRegs, Reg_F)) 99 val vecFreeList = Module(new StdFreeList(VfPhyRegs - VecLogicRegs, VecLogicRegs, Reg_V, 31)) 100 val v0FreeList = Module(new StdFreeList(V0PhyRegs - V0LogicRegs, V0LogicRegs, Reg_V0, 1)) 101 val vlFreeList = Module(new StdFreeList(VlPhyRegs - VlLogicRegs, VlLogicRegs, Reg_Vl, 1)) 102 103 104 intFreeList.io.commit <> io.rabCommits 105 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 106 fpFreeList.io.commit <> io.rabCommits 107 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 108 vecFreeList.io.commit <> io.rabCommits 109 vecFreeList.io.debug_rat.foreach(_ <> io.debug_vec_rat.get) 110 v0FreeList.io.commit <> io.rabCommits 111 v0FreeList.io.debug_rat.foreach(_ <> io.debug_v0_rat.get) 112 vlFreeList.io.commit <> io.rabCommits 113 vlFreeList.io.debug_rat.foreach(_ <> io.debug_vl_rat.get) 114 115 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 116 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 117 case Reg_I => x.rfWen && x.ldest =/= 0.U 118 case Reg_F => x.fpWen 119 case Reg_V => x.vecWen 120 case Reg_V0 => x.v0Wen 121 case Reg_Vl => x.vlWen 122 } 123 def needDestRegCommit[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 124 reg_t match { 125 case Reg_I => x.rfWen 126 case Reg_F => x.fpWen 127 case Reg_V => x.vecWen 128 case Reg_V0 => x.v0Wen 129 case Reg_Vl => x.vlWen 130 } 131 } 132 def needDestRegWalk[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 133 reg_t match { 134 case Reg_I => x.rfWen && x.ldest =/= 0.U 135 case Reg_F => x.fpWen 136 case Reg_V => x.vecWen 137 case Reg_V0 => x.v0Wen 138 case Reg_Vl => x.vlWen 139 } 140 } 141 142 // connect [redirect + walk] ports for fp & vec & int free list 143 Seq(fpFreeList, vecFreeList, intFreeList, v0FreeList, vlFreeList).foreach { case fl => 144 fl.io.redirect := io.redirect.valid 145 fl.io.walk := io.rabCommits.isWalk 146 } 147 // only when all free list and dispatch1 has enough space can we do allocation 148 // when isWalk, freelist can definitely allocate 149 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 150 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 151 vecFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 152 v0FreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 153 vlFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 154 155 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ vec free list ready ++ not walk 156 val canOut = dispatchCanAcc && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 157 158 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 159 sink.valid := source.valid 160 sink.bits := source.bits 161 } 162 val needRobFlags = compressUnit.io.out.needRobFlags 163 val instrSizesVec = compressUnit.io.out.instrSizes 164 val compressMasksVec = compressUnit.io.out.masks 165 166 // speculatively assign the instruction with an robIdx 167 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 168 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 169 val lastCycleMisprediction = GatedValidRegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 170 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 171 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 172 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 173 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 174 robIdxHead := robIdxHeadNext 175 176 /** 177 * Rename: allocate free physical register and update rename table 178 */ 179 val uops = Wire(Vec(RenameWidth, new DynInst)) 180 uops.foreach( uop => { 181 uop.srcState := DontCare 182 uop.debugInfo := DontCare 183 uop.lqIdx := DontCare 184 uop.sqIdx := DontCare 185 uop.waitForRobIdx := DontCare 186 uop.singleStep := DontCare 187 uop.snapshot := DontCare 188 uop.srcLoadDependency := DontCare 189 uop.numLsElem := DontCare 190 uop.hasException := DontCare 191 uop.useRegCache := DontCare 192 uop.regCacheIdx := DontCare 193 }) 194 private val fuType = uops.map(_.fuType) 195 private val fuOpType = uops.map(_.fuOpType) 196 private val vtype = uops.map(_.vpu.vtype) 197 private val sew = vtype.map(_.vsew) 198 private val lmul = vtype.map(_.vlmul) 199 private val eew = uops.map(_.vpu.veew) 200 private val mop = fuOpType.map(fuOpTypeItem => LSUOpType.getVecLSMop(fuOpTypeItem)) 201 private val isVlsType = fuType.map(fuTypeItem => isVls(fuTypeItem)) 202 private val isSegment = fuType.map(fuTypeItem => isVsegls(fuTypeItem)) 203 private val isUnitStride = fuOpType.map(fuOpTypeItem => LSUOpType.isAllUS(fuOpTypeItem)) 204 private val nf = fuOpType.zip(uops.map(_.vpu.nf)).map { case (fuOpTypeItem, nfItem) => Mux(LSUOpType.isWhole(fuOpTypeItem), 0.U, nfItem) } 205 private val mulBits = 3 // dirty code 206 private val emul = fuOpType.zipWithIndex.map { case (fuOpTypeItem, index) => 207 Mux( 208 LSUOpType.isWhole(fuOpTypeItem), 209 GenUSWholeEmul(nf(index)), 210 Mux( 211 LSUOpType.isMasked(fuOpTypeItem), 212 0.U(mulBits.W), 213 EewLog2(eew(index)) - sew(index) + lmul(index) 214 ) 215 ) 216 } 217 private val isVecUnitType = isVlsType.zip(isUnitStride).map { case (isVlsTypeItme, isUnitStrideItem) => 218 isVlsTypeItme && isUnitStrideItem 219 } 220 private val instType = isSegment.zip(mop).map { case (isSegementItem, mopItem) => Cat(isSegementItem, mopItem) } 221 // There is no way to calculate the 'flow' for 'unit-stride' exactly: 222 // Whether 'unit-stride' needs to be split can only be known after obtaining the address. 223 // For scalar instructions, this is not handled here, and different assignments are done later according to the situation. 224 private val numLsElem = instType.zipWithIndex.map { case (instTypeItem, index) => 225 Mux( 226 isVecUnitType(index), 227 VecMemUnitStrideMaxFlowNum.U, 228 GenRealFlowNum(instTypeItem, emul(index), lmul(index), eew(index), sew(index)) 229 ) 230 } 231 uops.zipWithIndex.map { case(u, i) => 232 u.numLsElem := Mux(io.in(i).valid & isVlsType(i), numLsElem(i), 0.U) 233 } 234 235 val needVecDest = Wire(Vec(RenameWidth, Bool())) 236 val needFpDest = Wire(Vec(RenameWidth, Bool())) 237 val needIntDest = Wire(Vec(RenameWidth, Bool())) 238 val needV0Dest = Wire(Vec(RenameWidth, Bool())) 239 val needVlDest = Wire(Vec(RenameWidth, Bool())) 240 private val inHeadValid = io.in.head.valid 241 242 val isMove = Wire(Vec(RenameWidth, Bool())) 243 isMove zip io.in.map(_.bits) foreach { 244 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 245 } 246 247 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 248 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 249 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 250 val walkNeedV0Dest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 251 val walkNeedVlDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 252 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 253 254 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 255 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 256 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 257 val v0SpecWen = Wire(Vec(RenameWidth, Bool())) 258 val vlSpecWen = Wire(Vec(RenameWidth, Bool())) 259 260 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 261 262 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 263 264 // uop calculation 265 for (i <- 0 until RenameWidth) { 266 (uops(i): Data).waiveAll :<= (io.in(i).bits: Data).waiveAll 267 268 // update cf according to ssit result 269 uops(i).storeSetHit := io.ssit(i).valid 270 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 271 uops(i).ssid := io.ssit(i).ssid 272 273 // update cf according to waittable result 274 uops(i).loadWaitBit := io.waittable(i) 275 276 uops(i).replayInst := false.B // set by IQ or MemQ 277 // alloc a new phy reg 278 needV0Dest(i) := io.in(i).valid && needDestReg(Reg_V0, io.in(i).bits) 279 needVlDest(i) := io.in(i).valid && needDestReg(Reg_Vl, io.in(i).bits) 280 needVecDest(i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 281 needFpDest(i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 282 needIntDest(i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 283 if (i < RabCommitWidth) { 284 walkNeedIntDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_I, io.rabCommits.info(i)) 285 walkNeedFpDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_F, io.rabCommits.info(i)) 286 walkNeedVecDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V, io.rabCommits.info(i)) 287 walkNeedV0Dest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V0, io.rabCommits.info(i)) 288 walkNeedVlDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_Vl, io.rabCommits.info(i)) 289 walkIsMove(i) := io.rabCommits.info(i).isMove 290 } 291 fpFreeList.io.allocateReq(i) := needFpDest(i) 292 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) 293 vecFreeList.io.allocateReq(i) := needVecDest(i) 294 vecFreeList.io.walkReq(i) := walkNeedVecDest(i) 295 v0FreeList.io.allocateReq(i) := needV0Dest(i) 296 v0FreeList.io.walkReq(i) := walkNeedV0Dest(i) 297 vlFreeList.io.allocateReq(i) := needVlDest(i) 298 vlFreeList.io.walkReq(i) := walkNeedVlDest(i) 299 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 300 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 301 302 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 303 io.in(i).ready := !io.in(0).valid || canOut 304 305 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 306 uops(i).instrSize := instrSizesVec(i) 307 val hasExceptionExceptFlushPipe = Cat(selectFrontend(uops(i).exceptionVec) :+ uops(i).exceptionVec(illegalInstr) :+ uops(i).exceptionVec(virtualInstr)).orR || uops(i).trigger.getFrontendCanFire 308 when(isMove(i) || hasExceptionExceptFlushPipe) { 309 uops(i).numUops := 0.U 310 uops(i).numWB := 0.U 311 } 312 if (i > 0) { 313 when(!needRobFlags(i - 1)) { 314 uops(i).firstUop := false.B 315 uops(i).ftqPtr := uops(i - 1).ftqPtr 316 uops(i).ftqOffset := uops(i - 1).ftqOffset 317 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 318 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 319 } 320 } 321 when(!needRobFlags(i)) { 322 uops(i).lastUop := false.B 323 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 324 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 325 } 326 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 327 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 328 // vector instructions' uopSplitType cannot be UopSplitType.SCA_SIM 329 uops(i).dirtyVs := (compressMasksVec(i) & Cat(io.in.map(_.bits.uopSplitType =/= UopSplitType.SCA_SIM).reverse)).orR 330 // psrc0,psrc1,psrc2 don't require v0ReadPorts because their srcType can distinguish whether they are V0 or not 331 uops(i).psrc(0) := Mux1H(uops(i).srcType(0)(2, 0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 332 uops(i).psrc(1) := Mux1H(uops(i).srcType(1)(2, 0), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 333 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 334 uops(i).psrc(3) := io.v0ReadPorts(i)(0) 335 uops(i).psrc(4) := io.vlReadPorts(i)(0) 336 337 // int psrc2 should be bypassed from next instruction if it is fused 338 if (i < RenameWidth - 1) { 339 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 340 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 341 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 342 uops(i).psrc(1) := 0.U 343 } 344 } 345 uops(i).eliminatedMove := isMove(i) 346 347 // update pdest 348 uops(i).pdest := MuxCase(0.U, Seq( 349 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 350 needFpDest(i) -> fpFreeList.io.allocatePhyReg(i), 351 needVecDest(i) -> vecFreeList.io.allocatePhyReg(i), 352 needV0Dest(i) -> v0FreeList.io.allocatePhyReg(i), 353 needVlDest(i) -> vlFreeList.io.allocatePhyReg(i), 354 )) 355 356 // Assign performance counters 357 uops(i).debugInfo.renameTime := GTimer() 358 359 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 360 io.out(i).bits := uops(i) 361 // Todo: move these shit in decode stage 362 // dirty code for fence. The lsrc is passed by imm. 363 when (io.out(i).bits.fuType === FuType.fence.U) { 364 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 365 } 366 367 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 368// when (io.in(i).bits.isSoftPrefetch) { 369// io.out(i).bits.fuType := FuType.ldu.U 370// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 371// io.out(i).bits.selImm := SelImm.IMM_S 372// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 373// } 374 375 // dirty code for lui+addi(w) fusion 376 if (i < RenameWidth - 1) { 377 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 378 when (fused_lui32) { 379 val lui_imm = io.in(i).bits.imm(19, 0) 380 val add_imm = io.in(i + 1).bits.imm(11, 0) 381 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + add_imm.getWidth) 382 io.out(i).bits.imm := Cat(lui_imm, add_imm) 383 } 384 } 385 386 // write speculative rename table 387 // we update rat later inside commit code 388 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 389 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 390 vecSpecWen(i) := needVecDest(i) && vecFreeList.io.canAllocate && vecFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 391 v0SpecWen(i) := needV0Dest(i) && v0FreeList.io.canAllocate && v0FreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 392 vlSpecWen(i) := needVlDest(i) && vlFreeList.io.canAllocate && vlFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 393 394 395 if (i < RabCommitWidth) { 396 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 397 walkPdest(i) := io.rabCommits.info(i).pdest 398 } else { 399 walkPdest(i) := io.out(i).bits.pdest 400 } 401 } 402 403 /** 404 * How to set psrc: 405 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 406 * - default: psrc from RAT 407 * How to set pdest: 408 * - Mux(isMove, psrc, pdest_from_freelist). 409 * 410 * The critical path of rename lies here: 411 * When move elimination is enabled, we need to update the rat with psrc. 412 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 413 * 414 * If we expand these logic for pdest(N): 415 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 416 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 417 * Mux(bypass(N, N - 2), pdest(N - 2), 418 * ... 419 * Mux(bypass(N, 0), pdest(0), 420 * rat_out(N))...)), 421 * freelist_out(N)) 422 */ 423 // a simple functional model for now 424 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 425 426 // psrc(n) + pdest(1) 427 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 428 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 429 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 430 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 431 for (i <- 1 until RenameWidth) { 432 val v0Cond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 433 if (i == 3) (s === SrcType.vp) || (s === SrcType.v0) 434 else false.B 435 } :+ needV0Dest(i) 436 val vlCond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 437 if (i == 4) s === SrcType.vp 438 else false.B 439 } :+ needVlDest(i) 440 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 441 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 442 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 443 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 444 for ((((((cond1, (condV0, condVl)), cond2), cond3), t), j) <- vecCond.zip(v0Cond.zip(vlCond)).zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 445 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 446 val indexMatch = in.bits.ldest === t 447 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 448 val v0vlMatch = condV0 && needV0Dest(j) || condVl && needVlDest(j) 449 indexMatch && writeMatch || v0vlMatch 450 } 451 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 452 } 453 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 454 (z, next) => Mux(next._2, next._1, z) 455 } 456 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 457 (z, next) => Mux(next._2, next._1, z) 458 } 459 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 460 (z, next) => Mux(next._2, next._1, z) 461 } 462 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 463 (z, next) => Mux(next._2, next._1, z) 464 } 465 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 466 (z, next) => Mux(next._2, next._1, z) 467 } 468 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 469 470 // Todo: better implementation for fields reuse 471 // For fused-lui-load, load.src(0) is replaced by the imm. 472 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 473 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 474 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 475 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 476 when (fused_lui_load) { 477 // The first LOAD operand (base address) is replaced by LUI-imm and stored in imm 478 val lui_imm = io.in(i - 1).bits.imm(ImmUnion.U.len - 1, 0) 479 val ld_imm = io.in(i).bits.imm(ImmUnion.I.len - 1, 0) 480 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + ld_imm.getWidth) 481 io.out(i).bits.srcType(0) := SrcType.imm 482 io.out(i).bits.imm := Cat(lui_imm, ld_imm) 483 } 484 485 } 486 487 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 488 val lastCycleCreateSnpt = RegInit(false.B) 489 lastCycleCreateSnpt := genSnapshot && !io.snptIsFull 490 val sameSnptDistance = (RobCommitWidth * 4).U 491 // notInSameSnpt: 1.robidxHead - snapLastEnq >= sameSnptDistance 2.no snap 492 val notInSameSnpt = GatedValidRegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= sameSnptDistance || !io.snptLastEnq.valid) 493 val allowSnpt = if (EnableRenameSnapshot) notInSameSnpt && !lastCycleCreateSnpt && io.in.head.bits.firstUop else false.B 494 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 495 io.out.map{ x => 496 x.bits.hasException := Cat(selectFrontend(x.bits.exceptionVec) :+ x.bits.exceptionVec(illegalInstr) :+ x.bits.exceptionVec(virtualInstr)).orR || x.bits.trigger.getFrontendCanFire 497 } 498 if(backendParams.debugEn){ 499 dontTouch(robIdxHeadNext) 500 dontTouch(notInSameSnpt) 501 dontTouch(genSnapshot) 502 } 503 intFreeList.io.snpt := io.snpt 504 fpFreeList.io.snpt := io.snpt 505 vecFreeList.io.snpt := io.snpt 506 v0FreeList.io.snpt := io.snpt 507 vlFreeList.io.snpt := io.snpt 508 intFreeList.io.snpt.snptEnq := genSnapshot 509 fpFreeList.io.snpt.snptEnq := genSnapshot 510 vecFreeList.io.snpt.snptEnq := genSnapshot 511 v0FreeList.io.snpt.snptEnq := genSnapshot 512 vlFreeList.io.snpt.snptEnq := genSnapshot 513 514 /** 515 * Instructions commit: update freelist and rename table 516 */ 517 for (i <- 0 until RabCommitWidth) { 518 val commitValid = io.rabCommits.isCommit && io.rabCommits.commitValid(i) 519 val walkValid = io.rabCommits.isWalk && io.rabCommits.walkValid(i) 520 521 // I. RAT Update 522 // When redirect happens (mis-prediction), don't update the rename table 523 io.intRenamePorts(i).wen := intSpecWen(i) 524 io.intRenamePorts(i).addr := uops(i).ldest(log2Ceil(IntLogicRegs) - 1, 0) 525 io.intRenamePorts(i).data := io.out(i).bits.pdest 526 527 io.fpRenamePorts(i).wen := fpSpecWen(i) 528 io.fpRenamePorts(i).addr := uops(i).ldest(log2Ceil(FpLogicRegs) - 1, 0) 529 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 530 531 io.vecRenamePorts(i).wen := vecSpecWen(i) 532 io.vecRenamePorts(i).addr := uops(i).ldest(log2Ceil(VecLogicRegs) - 1, 0) 533 io.vecRenamePorts(i).data := vecFreeList.io.allocatePhyReg(i) 534 535 io.v0RenamePorts(i).wen := v0SpecWen(i) 536 io.v0RenamePorts(i).addr := uops(i).ldest(log2Ceil(V0LogicRegs) - 1, 0) 537 io.v0RenamePorts(i).data := v0FreeList.io.allocatePhyReg(i) 538 539 io.vlRenamePorts(i).wen := vlSpecWen(i) 540 io.vlRenamePorts(i).addr := uops(i).ldest(log2Ceil(VlLogicRegs) - 1, 0) 541 io.vlRenamePorts(i).data := vlFreeList.io.allocatePhyReg(i) 542 543 // II. Free List Update 544 intFreeList.io.freeReq(i) := io.int_need_free(i) 545 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 546 fpFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_F, io.rabCommits.info(i))) 547 fpFreeList.io.freePhyReg(i) := io.fp_old_pdest(i) 548 vecFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V, io.rabCommits.info(i))) 549 vecFreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 550 v0FreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V0, io.rabCommits.info(i))) 551 v0FreeList.io.freePhyReg(i) := io.v0_old_pdest(i) 552 vlFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_Vl, io.rabCommits.info(i))) 553 vlFreeList.io.freePhyReg(i) := io.vl_old_pdest(i) 554 } 555 556 /* 557 Debug and performance counters 558 */ 559 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 560 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 561 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 562 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 563 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 564 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 565 ) 566 } 567 568 for ((x,y) <- io.in.zip(io.out)) { 569 printRenameInfo(x, y) 570 } 571 572 io.out.map { case x => 573 when(x.valid && x.bits.rfWen){ 574 assert(x.bits.ldest =/= 0.U, "rfWen cannot be 1 when Int regfile ldest is 0") 575 } 576 } 577 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 578 // bad speculation 579 val recStall = io.redirect.valid || io.rabCommits.isWalk 580 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.rabCommits.isWalk && debugRedirect.debugIsCtrl) 581 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.rabCommits.isWalk && debugRedirect.debugIsMemVio) 582 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 583 XSPerfAccumulate("recovery_stall", recStall) 584 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 585 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 586 XSPerfAccumulate("other_recovery_stall", otherRecStall) 587 // freelist stall 588 val notRecStall = !io.out.head.valid && !recStall 589 val intFlStall = notRecStall && inHeadValid && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 590 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 591 val vecFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 592 val v0FlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 593 val vlFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 594 val multiFlStall = notRecStall && inHeadValid && (PopCount(Cat( 595 !intFreeList.io.canAllocate, 596 !fpFreeList.io.canAllocate, 597 !vecFreeList.io.canAllocate, 598 !v0FreeList.io.canAllocate, 599 !vlFreeList.io.canAllocate, 600 )) > 1.U) 601 // other stall 602 val otherStall = notRecStall && !intFlStall && !fpFlStall && !vecFlStall && !v0FlStall && !vlFlStall && !multiFlStall 603 604 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 605 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 606 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 607 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 608 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 609 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 610 intFlStall -> TopDownCounters.IntFlStall.id.U, 611 fpFlStall -> TopDownCounters.FpFlStall.id.U, 612 vecFlStall -> TopDownCounters.VecFlStall.id.U, 613 v0FlStall -> TopDownCounters.V0FlStall.id.U, 614 vlFlStall -> TopDownCounters.VlFlStall.id.U, 615 multiFlStall -> TopDownCounters.MultiFlStall.id.U, 616 ) 617 )) 618 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 619 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 620 } 621 622 XSDebug(io.rabCommits.isWalk, p"Walk Recovery Enabled\n") 623 XSDebug(io.rabCommits.isWalk, p"validVec:${Binary(io.rabCommits.walkValid.asUInt)}\n") 624 for (i <- 0 until RabCommitWidth) { 625 val info = io.rabCommits.info(i) 626 XSDebug(io.rabCommits.isWalk && io.rabCommits.walkValid(i), p"[#$i walk info] " + 627 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen} v0Wen:${info.v0Wen} vlWen:${info.vlWen}") 628 } 629 630 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 631 632 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 633 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 634 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 635 XSPerfAccumulate("wait_cycle", !io.in.head.valid && dispatchCanAcc) 636 637 // These stall reasons could overlap each other, but we configure the priority as fellows. 638 // walk stall > dispatch stall > int freelist stall > fp freelist stall 639 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 640 private val stallForWalk = inHeadValid && io.rabCommits.isWalk 641 private val stallForDispatch = inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc 642 private val stallForIntFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 643 private val stallForFpFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 644 private val stallForVecFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 645 private val stallForV0FL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 646 private val stallForVlFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 647 XSPerfAccumulate("stall_cycle", inHeadStall) 648 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 649 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 650 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 651 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 652 XSPerfAccumulate("stall_cycle_vec", stallForVecFL) 653 XSPerfAccumulate("stall_cycle_vec", stallForV0FL) 654 XSPerfAccumulate("stall_cycle_vec", stallForVlFL) 655 656 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 657 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 658 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 659 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 660 661 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 662 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 663 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 664 665 val renamePerf = Seq( 666 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 667 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 668 ("rename_stall ", inHeadStall), 669 ("rename_stall_cycle_walk ", inHeadValid && io.rabCommits.isWalk), 670 ("rename_stall_cycle_dispatch", inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc), 671 ("rename_stall_cycle_int ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate), 672 ("rename_stall_cycle_fp ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 673 ("rename_stall_cycle_vec ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate), 674 ("rename_stall_cycle_v0 ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate), 675 ("rename_stall_cycle_vl ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate), 676 ) 677 val intFlPerf = intFreeList.getPerfEvents 678 val fpFlPerf = fpFreeList.getPerfEvents 679 val vecFlPerf = vecFreeList.getPerfEvents 680 val v0FlPerf = v0FreeList.getPerfEvents 681 val vlFlPerf = vlFreeList.getPerfEvents 682 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf ++ vecFlPerf ++ v0FlPerf ++ vlFlPerf 683 generatePerfEvent() 684} 685