1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.{RobEnqIO, RobPtr} 30import xiangshan.mem.mdp._ 31import xiangshan.ExceptionNO._ 32 33class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 34 35 // params alias 36 private val numRegSrc = backendParams.numRegSrc 37 private val numVecRegSrc = backendParams.numVecRegSrc 38 private val numVecRatPorts = numVecRegSrc 39 40 println(s"[Rename] numRegSrc: $numRegSrc") 41 42 val io = IO(new Bundle() { 43 val redirect = Flipped(ValidIO(new Redirect)) 44 val rabCommits = Input(new RabCommitIO) 45 // from decode 46 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 47 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 48 // ssit read result 49 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 50 // waittable read result 51 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 52 // to rename table 53 val intReadPorts = Vec(RenameWidth, Vec(2, Input(UInt(PhyRegIdxWidth.W)))) 54 val fpReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 55 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 56 val v0ReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 57 val vlReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 58 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 59 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 60 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 61 val v0RenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 62 val vlRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 63 // from rename table 64 val int_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 65 val fp_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 66 val vec_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 67 val v0_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 68 val vl_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 69 val int_need_free = Vec(RabCommitWidth, Input(Bool())) 70 // to dispatch1 71 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 72 // for snapshots 73 val snpt = Input(new SnapshotPort) 74 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 75 val snptIsFull= Input(Bool()) 76 // debug arch ports 77 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 78 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 79 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Input(UInt(PhyRegIdxWidth.W)))) else None 80 val debug_v0_rat = if (backendParams.debugEn) Some(Vec(1, Input(UInt(PhyRegIdxWidth.W)))) else None 81 val debug_vl_rat = if (backendParams.debugEn) Some(Vec(1, Input(UInt(PhyRegIdxWidth.W)))) else None 82 // perf only 83 val stallReason = new Bundle { 84 val in = Flipped(new StallReasonIO(RenameWidth)) 85 val out = new StallReasonIO(RenameWidth) 86 } 87 }) 88 89 // io alias 90 private val dispatchCanAcc = io.out.head.ready 91 92 val compressUnit = Module(new CompressUnit()) 93 // create free list and rat 94 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 95 val fpFreeList = Module(new StdFreeList(FpPhyRegs - FpLogicRegs, FpLogicRegs, Reg_F)) 96 val vecFreeList = Module(new StdFreeList(VfPhyRegs - VecLogicRegs, VecLogicRegs, Reg_V, 31)) 97 val v0FreeList = Module(new StdFreeList(V0PhyRegs - V0LogicRegs, V0LogicRegs, Reg_V0, 1)) 98 val vlFreeList = Module(new StdFreeList(VlPhyRegs - VlLogicRegs, VlLogicRegs, Reg_Vl, 1)) 99 100 101 intFreeList.io.commit <> io.rabCommits 102 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 103 fpFreeList.io.commit <> io.rabCommits 104 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 105 vecFreeList.io.commit <> io.rabCommits 106 vecFreeList.io.debug_rat.foreach(_ <> io.debug_vec_rat.get) 107 v0FreeList.io.commit <> io.rabCommits 108 v0FreeList.io.debug_rat.foreach(_ <> io.debug_v0_rat.get) 109 vlFreeList.io.commit <> io.rabCommits 110 vlFreeList.io.debug_rat.foreach(_ <> io.debug_vl_rat.get) 111 112 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 113 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 114 case Reg_I => x.rfWen && x.ldest =/= 0.U 115 case Reg_F => x.fpWen 116 case Reg_V => x.vecWen 117 case Reg_V0 => x.v0Wen 118 case Reg_Vl => x.vlWen 119 } 120 def needDestRegCommit[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 121 reg_t match { 122 case Reg_I => x.rfWen 123 case Reg_F => x.fpWen 124 case Reg_V => x.vecWen 125 case Reg_V0 => x.v0Wen 126 case Reg_Vl => x.vlWen 127 } 128 } 129 def needDestRegWalk[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 130 reg_t match { 131 case Reg_I => x.rfWen && x.ldest =/= 0.U 132 case Reg_F => x.fpWen 133 case Reg_V => x.vecWen 134 case Reg_V0 => x.v0Wen 135 case Reg_Vl => x.vlWen 136 } 137 } 138 139 // connect [redirect + walk] ports for fp & vec & int free list 140 Seq(fpFreeList, vecFreeList, intFreeList, v0FreeList, vlFreeList).foreach { case fl => 141 fl.io.redirect := io.redirect.valid 142 fl.io.walk := io.rabCommits.isWalk 143 } 144 // only when all free list and dispatch1 has enough space can we do allocation 145 // when isWalk, freelist can definitely allocate 146 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 147 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 148 vecFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 149 v0FreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 150 vlFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 151 152 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ vec free list ready ++ not walk 153 val canOut = dispatchCanAcc && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 154 155 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 156 sink.valid := source.valid 157 sink.bits := source.bits 158 } 159 val needRobFlags = compressUnit.io.out.needRobFlags 160 val instrSizesVec = compressUnit.io.out.instrSizes 161 val compressMasksVec = compressUnit.io.out.masks 162 163 // speculatively assign the instruction with an robIdx 164 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 165 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 166 val lastCycleMisprediction = GatedValidRegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 167 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 168 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 169 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 170 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 171 robIdxHead := robIdxHeadNext 172 173 /** 174 * Rename: allocate free physical register and update rename table 175 */ 176 val uops = Wire(Vec(RenameWidth, new DynInst)) 177 uops.foreach( uop => { 178 uop.srcState := DontCare 179 uop.debugInfo := DontCare 180 uop.lqIdx := DontCare 181 uop.sqIdx := DontCare 182 uop.waitForRobIdx := DontCare 183 uop.singleStep := DontCare 184 uop.snapshot := DontCare 185 uop.srcLoadDependency := DontCare 186 uop.numLsElem := DontCare 187 uop.hasException := DontCare 188 }) 189 190 val needVecDest = Wire(Vec(RenameWidth, Bool())) 191 val needFpDest = Wire(Vec(RenameWidth, Bool())) 192 val needIntDest = Wire(Vec(RenameWidth, Bool())) 193 val needV0Dest = Wire(Vec(RenameWidth, Bool())) 194 val needVlDest = Wire(Vec(RenameWidth, Bool())) 195 val hasValid = Cat(io.in.map(_.valid)).orR 196 private val inHeadValid = io.in.head.valid 197 198 val isMove = Wire(Vec(RenameWidth, Bool())) 199 isMove zip io.in.map(_.bits) foreach { 200 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 201 } 202 203 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 204 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 205 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 206 val walkNeedV0Dest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 207 val walkNeedVlDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 208 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 209 210 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 211 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 212 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 213 val v0SpecWen = Wire(Vec(RenameWidth, Bool())) 214 val vlSpecWen = Wire(Vec(RenameWidth, Bool())) 215 216 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 217 218 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 219 220 // uop calculation 221 for (i <- 0 until RenameWidth) { 222 (uops(i): Data).waiveAll :<= (io.in(i).bits: Data).waiveAll 223 224 // update cf according to ssit result 225 uops(i).storeSetHit := io.ssit(i).valid 226 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 227 uops(i).ssid := io.ssit(i).ssid 228 229 // update cf according to waittable result 230 uops(i).loadWaitBit := io.waittable(i) 231 232 uops(i).replayInst := false.B // set by IQ or MemQ 233 // alloc a new phy reg 234 needV0Dest(i) := io.in(i).valid && needDestReg(Reg_V0, io.in(i).bits) 235 needVlDest(i) := io.in(i).valid && needDestReg(Reg_Vl, io.in(i).bits) 236 needVecDest(i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 237 needFpDest(i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 238 needIntDest(i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 239 if (i < RabCommitWidth) { 240 walkNeedIntDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_I, io.rabCommits.info(i)) 241 walkNeedFpDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_F, io.rabCommits.info(i)) 242 walkNeedVecDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V, io.rabCommits.info(i)) 243 walkNeedV0Dest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V0, io.rabCommits.info(i)) 244 walkNeedVlDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_Vl, io.rabCommits.info(i)) 245 walkIsMove(i) := io.rabCommits.info(i).isMove 246 } 247 fpFreeList.io.allocateReq(i) := needFpDest(i) 248 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) 249 vecFreeList.io.allocateReq(i) := needVecDest(i) 250 vecFreeList.io.walkReq(i) := walkNeedVecDest(i) 251 v0FreeList.io.allocateReq(i) := needV0Dest(i) 252 v0FreeList.io.walkReq(i) := walkNeedV0Dest(i) 253 vlFreeList.io.allocateReq(i) := needVlDest(i) 254 vlFreeList.io.walkReq(i) := walkNeedVlDest(i) 255 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 256 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 257 258 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 259 io.in(i).ready := !hasValid || canOut 260 261 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 262 uops(i).instrSize := instrSizesVec(i) 263 when(isMove(i)) { 264 uops(i).numUops := 0.U 265 uops(i).numWB := 0.U 266 } 267 if (i > 0) { 268 when(!needRobFlags(i - 1)) { 269 uops(i).firstUop := false.B 270 uops(i).ftqPtr := uops(i - 1).ftqPtr 271 uops(i).ftqOffset := uops(i - 1).ftqOffset 272 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 273 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 274 } 275 } 276 when(!needRobFlags(i)) { 277 uops(i).lastUop := false.B 278 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 279 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 280 } 281 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 282 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 283 // vector instructions' uopSplitType cannot be UopSplitType.SCA_SIM 284 uops(i).dirtyVs := (compressMasksVec(i) & Cat(io.in.map(_.bits.uopSplitType =/= UopSplitType.SCA_SIM).reverse)).orR 285 // psrc0,psrc1,psrc2 don't require v0ReadPorts because their srcType can distinguish whether they are V0 or not 286 uops(i).psrc(0) := Mux1H(uops(i).srcType(0)(2, 0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 287 uops(i).psrc(1) := Mux1H(uops(i).srcType(1)(2, 0), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 288 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 289 uops(i).psrc(3) := io.v0ReadPorts(i)(0) 290 uops(i).psrc(4) := io.vlReadPorts(i)(0) 291 292 // int psrc2 should be bypassed from next instruction if it is fused 293 if (i < RenameWidth - 1) { 294 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 295 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 296 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 297 uops(i).psrc(1) := 0.U 298 } 299 } 300 uops(i).eliminatedMove := isMove(i) 301 302 // update pdest 303 uops(i).pdest := MuxCase(0.U, Seq( 304 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 305 needFpDest(i) -> fpFreeList.io.allocatePhyReg(i), 306 needVecDest(i) -> vecFreeList.io.allocatePhyReg(i), 307 needV0Dest(i) -> v0FreeList.io.allocatePhyReg(i), 308 needVlDest(i) -> vlFreeList.io.allocatePhyReg(i), 309 )) 310 311 // Assign performance counters 312 uops(i).debugInfo.renameTime := GTimer() 313 314 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 315 io.out(i).bits := uops(i) 316 // Todo: move these shit in decode stage 317 // dirty code for fence. The lsrc is passed by imm. 318 when (io.out(i).bits.fuType === FuType.fence.U) { 319 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 320 } 321 322 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 323// when (io.in(i).bits.isSoftPrefetch) { 324// io.out(i).bits.fuType := FuType.ldu.U 325// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 326// io.out(i).bits.selImm := SelImm.IMM_S 327// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 328// } 329 330 // dirty code for lui+addi(w) fusion 331 if (i < RenameWidth - 1) { 332 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 333 when (fused_lui32) { 334 val lui_imm = io.in(i).bits.imm(19, 0) 335 val add_imm = io.in(i + 1).bits.imm(11, 0) 336 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + add_imm.getWidth) 337 io.out(i).bits.imm := Cat(lui_imm, add_imm) 338 } 339 } 340 341 // write speculative rename table 342 // we update rat later inside commit code 343 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 344 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 345 vecSpecWen(i) := needVecDest(i) && vecFreeList.io.canAllocate && vecFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 346 v0SpecWen(i) := needV0Dest(i) && v0FreeList.io.canAllocate && v0FreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 347 vlSpecWen(i) := needVlDest(i) && vlFreeList.io.canAllocate && vlFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 348 349 350 if (i < RabCommitWidth) { 351 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 352 walkPdest(i) := io.rabCommits.info(i).pdest 353 } else { 354 walkPdest(i) := io.out(i).bits.pdest 355 } 356 } 357 358 /** 359 * How to set psrc: 360 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 361 * - default: psrc from RAT 362 * How to set pdest: 363 * - Mux(isMove, psrc, pdest_from_freelist). 364 * 365 * The critical path of rename lies here: 366 * When move elimination is enabled, we need to update the rat with psrc. 367 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 368 * 369 * If we expand these logic for pdest(N): 370 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 371 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 372 * Mux(bypass(N, N - 2), pdest(N - 2), 373 * ... 374 * Mux(bypass(N, 0), pdest(0), 375 * rat_out(N))...)), 376 * freelist_out(N)) 377 */ 378 // a simple functional model for now 379 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 380 381 // psrc(n) + pdest(1) 382 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 383 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 384 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 385 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 386 for (i <- 1 until RenameWidth) { 387 val v0Cond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 388 if (i == 3) (s === SrcType.vp) || (s === SrcType.v0) 389 else false.B 390 } :+ needV0Dest(i) 391 val vlCond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 392 if (i == 4) s === SrcType.vp 393 else false.B 394 } :+ needVlDest(i) 395 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 396 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 397 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 398 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 399 for ((((((cond1, (condV0, condVl)), cond2), cond3), t), j) <- vecCond.zip(v0Cond.zip(vlCond)).zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 400 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 401 val indexMatch = in.bits.ldest === t 402 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 403 val v0vlMatch = condV0 && needV0Dest(j) || condVl && needVlDest(j) 404 indexMatch && writeMatch || v0vlMatch 405 } 406 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 407 } 408 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 409 (z, next) => Mux(next._2, next._1, z) 410 } 411 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 412 (z, next) => Mux(next._2, next._1, z) 413 } 414 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 415 (z, next) => Mux(next._2, next._1, z) 416 } 417 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 418 (z, next) => Mux(next._2, next._1, z) 419 } 420 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 421 (z, next) => Mux(next._2, next._1, z) 422 } 423 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 424 425 // Todo: better implementation for fields reuse 426 // For fused-lui-load, load.src(0) is replaced by the imm. 427 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 428 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 429 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 430 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 431 when (fused_lui_load) { 432 // The first LOAD operand (base address) is replaced by LUI-imm and stored in imm 433 val lui_imm = io.in(i - 1).bits.imm(ImmUnion.U.len - 1, 0) 434 val ld_imm = io.in(i).bits.imm(ImmUnion.I.len - 1, 0) 435 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + ld_imm.getWidth) 436 io.out(i).bits.srcType(0) := SrcType.imm 437 io.out(i).bits.imm := Cat(lui_imm, ld_imm) 438 } 439 440 } 441 442 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 443 val lastCycleCreateSnpt = RegInit(false.B) 444 lastCycleCreateSnpt := genSnapshot && !io.snptIsFull 445 val sameSnptDistance = (RobCommitWidth * 4).U 446 // notInSameSnpt: 1.robidxHead - snapLastEnq >= sameSnptDistance 2.no snap 447 val notInSameSnpt = GatedValidRegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= sameSnptDistance || !io.snptLastEnq.valid) 448 val allowSnpt = if (EnableRenameSnapshot) notInSameSnpt && !lastCycleCreateSnpt && io.in.head.bits.firstUop else false.B 449 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 450 io.out.map{ x => 451 x.bits.hasException := Cat(selectFrontend(x.bits.exceptionVec) :+ x.bits.exceptionVec(illegalInstr) :+ x.bits.exceptionVec(virtualInstr)).orR || x.bits.trigger.getFrontendCanFire 452 } 453 if(backendParams.debugEn){ 454 dontTouch(robIdxHeadNext) 455 dontTouch(notInSameSnpt) 456 dontTouch(genSnapshot) 457 } 458 intFreeList.io.snpt := io.snpt 459 fpFreeList.io.snpt := io.snpt 460 vecFreeList.io.snpt := io.snpt 461 v0FreeList.io.snpt := io.snpt 462 vlFreeList.io.snpt := io.snpt 463 intFreeList.io.snpt.snptEnq := genSnapshot 464 fpFreeList.io.snpt.snptEnq := genSnapshot 465 vecFreeList.io.snpt.snptEnq := genSnapshot 466 v0FreeList.io.snpt.snptEnq := genSnapshot 467 vlFreeList.io.snpt.snptEnq := genSnapshot 468 469 /** 470 * Instructions commit: update freelist and rename table 471 */ 472 for (i <- 0 until RabCommitWidth) { 473 val commitValid = io.rabCommits.isCommit && io.rabCommits.commitValid(i) 474 val walkValid = io.rabCommits.isWalk && io.rabCommits.walkValid(i) 475 476 // I. RAT Update 477 // When redirect happens (mis-prediction), don't update the rename table 478 io.intRenamePorts(i).wen := intSpecWen(i) 479 io.intRenamePorts(i).addr := uops(i).ldest 480 io.intRenamePorts(i).data := io.out(i).bits.pdest 481 482 io.fpRenamePorts(i).wen := fpSpecWen(i) 483 io.fpRenamePorts(i).addr := uops(i).ldest 484 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 485 486 io.vecRenamePorts(i).wen := vecSpecWen(i) 487 io.vecRenamePorts(i).addr := uops(i).ldest 488 io.vecRenamePorts(i).data := vecFreeList.io.allocatePhyReg(i) 489 490 io.v0RenamePorts(i).wen := v0SpecWen(i) 491 io.v0RenamePorts(i).addr := uops(i).ldest 492 io.v0RenamePorts(i).data := v0FreeList.io.allocatePhyReg(i) 493 494 io.vlRenamePorts(i).wen := vlSpecWen(i) 495 io.vlRenamePorts(i).addr := uops(i).ldest 496 io.vlRenamePorts(i).data := vlFreeList.io.allocatePhyReg(i) 497 498 // II. Free List Update 499 intFreeList.io.freeReq(i) := io.int_need_free(i) 500 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 501 fpFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_F, io.rabCommits.info(i))) 502 fpFreeList.io.freePhyReg(i) := io.fp_old_pdest(i) 503 vecFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V, io.rabCommits.info(i))) 504 vecFreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 505 v0FreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V0, io.rabCommits.info(i))) 506 v0FreeList.io.freePhyReg(i) := io.v0_old_pdest(i) 507 vlFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_Vl, io.rabCommits.info(i))) 508 vlFreeList.io.freePhyReg(i) := io.vl_old_pdest(i) 509 } 510 511 /* 512 Debug and performance counters 513 */ 514 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 515 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 516 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 517 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 518 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 519 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 520 ) 521 } 522 523 for ((x,y) <- io.in.zip(io.out)) { 524 printRenameInfo(x, y) 525 } 526 527 io.out.map { case x => 528 when(x.valid && x.bits.rfWen){ 529 assert(x.bits.ldest =/= 0.U, "rfWen cannot be 1 when Int regfile ldest is 0") 530 } 531 } 532 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 533 // bad speculation 534 val recStall = io.redirect.valid || io.rabCommits.isWalk 535 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.rabCommits.isWalk && debugRedirect.debugIsCtrl) 536 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.rabCommits.isWalk && debugRedirect.debugIsMemVio) 537 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 538 XSPerfAccumulate("recovery_stall", recStall) 539 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 540 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 541 XSPerfAccumulate("other_recovery_stall", otherRecStall) 542 // freelist stall 543 val notRecStall = !io.out.head.valid && !recStall 544 val intFlStall = notRecStall && inHeadValid && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 545 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 546 val vecFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 547 val v0FlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 548 val vlFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 549 val multiFlStall = notRecStall && inHeadValid && (PopCount(Cat( 550 !intFreeList.io.canAllocate, 551 !fpFreeList.io.canAllocate, 552 !vecFreeList.io.canAllocate, 553 !v0FreeList.io.canAllocate, 554 !vlFreeList.io.canAllocate, 555 )) > 1.U) 556 // other stall 557 val otherStall = notRecStall && !intFlStall && !fpFlStall && !vecFlStall && !v0FlStall && !vlFlStall && !multiFlStall 558 559 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 560 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 561 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 562 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 563 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 564 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 565 intFlStall -> TopDownCounters.IntFlStall.id.U, 566 fpFlStall -> TopDownCounters.FpFlStall.id.U, 567 vecFlStall -> TopDownCounters.VecFlStall.id.U, 568 v0FlStall -> TopDownCounters.V0FlStall.id.U, 569 vlFlStall -> TopDownCounters.VlFlStall.id.U, 570 multiFlStall -> TopDownCounters.MultiFlStall.id.U, 571 ) 572 )) 573 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 574 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 575 } 576 577 XSDebug(io.rabCommits.isWalk, p"Walk Recovery Enabled\n") 578 XSDebug(io.rabCommits.isWalk, p"validVec:${Binary(io.rabCommits.walkValid.asUInt)}\n") 579 for (i <- 0 until RabCommitWidth) { 580 val info = io.rabCommits.info(i) 581 XSDebug(io.rabCommits.isWalk && io.rabCommits.walkValid(i), p"[#$i walk info] " + 582 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen} v0Wen:${info.v0Wen} vlWen:${info.vlWen}") 583 } 584 585 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 586 587 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 588 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 589 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 590 XSPerfAccumulate("wait_cycle", !io.in.head.valid && dispatchCanAcc) 591 592 // These stall reasons could overlap each other, but we configure the priority as fellows. 593 // walk stall > dispatch stall > int freelist stall > fp freelist stall 594 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 595 private val stallForWalk = inHeadValid && io.rabCommits.isWalk 596 private val stallForDispatch = inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc 597 private val stallForIntFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 598 private val stallForFpFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 599 private val stallForVecFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 600 private val stallForV0FL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 601 private val stallForVlFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 602 XSPerfAccumulate("stall_cycle", inHeadStall) 603 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 604 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 605 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 606 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 607 XSPerfAccumulate("stall_cycle_vec", stallForVecFL) 608 XSPerfAccumulate("stall_cycle_vec", stallForV0FL) 609 XSPerfAccumulate("stall_cycle_vec", stallForVlFL) 610 611 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 612 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 613 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 614 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 615 616 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 617 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 618 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 619 620 val renamePerf = Seq( 621 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 622 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 623 ("rename_stall ", inHeadStall), 624 ("rename_stall_cycle_walk ", inHeadValid && io.rabCommits.isWalk), 625 ("rename_stall_cycle_dispatch", inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc), 626 ("rename_stall_cycle_int ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate), 627 ("rename_stall_cycle_fp ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 628 ("rename_stall_cycle_vec ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate), 629 ("rename_stall_cycle_v0 ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate), 630 ("rename_stall_cycle_vl ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate), 631 ) 632 val intFlPerf = intFreeList.getPerfEvents 633 val fpFlPerf = fpFreeList.getPerfEvents 634 val vecFlPerf = vecFreeList.getPerfEvents 635 val v0FlPerf = v0FreeList.getPerfEvents 636 val vlFlPerf = vlFreeList.getPerfEvents 637 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf ++ vecFlPerf ++ v0FlPerf ++ vlFlPerf 638 generatePerfEvent() 639} 640