1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.{ParallelOR, XSDebug} 7 8class BusyTableReadIO extends XSBundle { 9 val req = Input(UInt(PhyRegIdxWidth.W)) 10 val resp = Output(Bool()) 11} 12 13class BusyTable(numReadPorts: Int, numWritePorts: Int) extends XSModule { 14 val io = IO(new Bundle() { 15 val flush = Input(Bool()) 16 // set preg state to busy 17 val allocPregs = Vec(RenameWidth, Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 18 // set preg state to ready (write back regfile + roq walk) 19 val wbPregs = Vec(numWritePorts, Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 20 // read preg state 21 val read = Vec(numReadPorts, new BusyTableReadIO) 22 }) 23 24 val table = RegInit(0.U(NRPhyRegs.W)) 25 26 def reqVecToMask(rVec: Vec[Valid[UInt]]): UInt = { 27 ParallelOR(rVec.map(v => Mux(v.valid, UIntToOH(v.bits), 0.U))) 28 } 29 30 val wbMask = reqVecToMask(io.wbPregs) 31 val allocMask = reqVecToMask(io.allocPregs) 32 33 val tableAfterWb = table & (~wbMask).asUInt 34 val tableAfterAlloc = tableAfterWb | allocMask 35 36 io.read.map(r => r.resp := !table(r.req)) 37 38 table := tableAfterAlloc 39 40 when(io.flush){ 41 table := 0.U(NRPhyRegs.W) 42 } 43 44 XSDebug(p"table : ${Binary(table)}\n") 45 XSDebug(p"tableNext: ${Binary(tableAfterAlloc)}\n") 46 XSDebug(p"allocMask: ${Binary(allocMask)}\n") 47 XSDebug(p"wbMask : ${Binary(wbMask)}\n") 48 for (i <- 0 until NRPhyRegs) { 49 XSDebug(table(i), "%d is busy\n", i.U) 50 } 51} 52