1package xiangshan.backend.regfile 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6 7class RfReadPort(len: Int) extends XSBundle { 8 val addr = Input(UInt(PhyRegIdxWidth.W)) 9 val data = Output(UInt(len.W)) 10 override def cloneType: RfReadPort.this.type = 11 new RfReadPort(len).asInstanceOf[this.type] 12} 13 14class RfWritePort(len: Int) extends XSBundle { 15 val wen = Input(Bool()) 16 val addr = Input(UInt(PhyRegIdxWidth.W)) 17 val data = Input(UInt(len.W)) 18 override def cloneType: RfWritePort.this.type = 19 new RfWritePort(len).asInstanceOf[this.type] 20} 21 22class Regfile 23( 24 numReadPorts: Int, 25 numWirtePorts: Int, 26 hasZero: Boolean, 27 len: Int 28) extends XSModule { 29 val io = IO(new Bundle() { 30 val readPorts = Vec(numReadPorts, new RfReadPort(len)) 31 val writePorts = Vec(numWirtePorts, new RfWritePort(len)) 32 }) 33 34 val useBlackBox = false 35 if (!useBlackBox) { 36 val mem = Mem(NRPhyRegs, UInt(len.W)) 37 for (r <- io.readPorts) { 38 val raddr_reg = RegNext(r.addr) 39 val rdata = if (hasZero) Mux(raddr_reg === 0.U, 0.U, mem(raddr_reg)) else mem(raddr_reg) 40 r.data := rdata 41 } 42 for (w <- io.writePorts) { 43 when(w.wen) { 44 mem(w.addr) := w.data 45 } 46 } 47 48 if (!env.FPGAPlatform) { 49 val debugArchRat = WireInit(VecInit(Seq.fill(32)(0.U(PhyRegIdxWidth.W)))) 50 ExcitingUtils.addSink( 51 debugArchRat, 52 if(hasZero) "DEBUG_INI_ARCH_RAT" else "DEBUG_FP_ARCH_RAT", 53 ExcitingUtils.Debug 54 ) 55 56 val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map( 57 x => if(hasZero){ 58 if(x._2 == 0) 0.U else mem(x._1) 59 } else { 60 ieee(mem(x._1)) 61 } 62 ))) 63 ExcitingUtils.addSource( 64 debugArchReg, 65 if(hasZero) "DEBUG_INT_ARCH_REG" else "DEBUG_FP_ARCH_REG", 66 ExcitingUtils.Debug 67 ) 68 } 69 } else { 70 71 val regfile = Module(new regfile_160x64_10w16r_sim) 72 73 regfile.io.clk := this.clock 74 regfile.io.gpr := hasZero.B 75 76 regfile.io.wen0 := io.writePorts(0).wen 77 regfile.io.waddr0 := io.writePorts(0).addr 78 regfile.io.wdata0 := io.writePorts(0).data 79 80 regfile.io.wen1 := io.writePorts(1).wen 81 regfile.io.waddr1 := io.writePorts(1).addr 82 regfile.io.wdata1 := io.writePorts(1).data 83 84 regfile.io.wen2 := io.writePorts(2).wen 85 regfile.io.waddr2 := io.writePorts(2).addr 86 regfile.io.wdata2 := io.writePorts(2).data 87 88 regfile.io.wen3 := io.writePorts(3).wen 89 regfile.io.waddr3 := io.writePorts(3).addr 90 regfile.io.wdata3 := io.writePorts(3).data 91 92 regfile.io.wen4 := io.writePorts(4).wen 93 regfile.io.waddr4 := io.writePorts(4).addr 94 regfile.io.wdata4 := io.writePorts(4).data 95 96 regfile.io.wen5 := io.writePorts(5).wen 97 regfile.io.waddr5 := io.writePorts(5).addr 98 regfile.io.wdata5 := io.writePorts(5).data 99 100 regfile.io.wen6 := io.writePorts(6).wen 101 regfile.io.waddr6 := io.writePorts(6).addr 102 regfile.io.wdata6 := io.writePorts(6).data 103 104 regfile.io.wen7 := io.writePorts(7).wen 105 regfile.io.waddr7 := io.writePorts(7).addr 106 regfile.io.wdata7 := io.writePorts(7).data 107 108 regfile.io.wen8 := false.B //io.writePorts(8).wen 109 regfile.io.waddr8 := DontCare //io.writePorts(8).addr 110 regfile.io.wdata8 := DontCare //io.writePorts(8).data 111 112 regfile.io.wen9 := false.B //io.writePorts(9).wen 113 regfile.io.waddr9 := DontCare //io.writePorts(9).addr 114 regfile.io.wdata9 := DontCare //io.writePorts(9).data 115 116 117 regfile.io.raddr0 := io.readPorts(0).addr 118 regfile.io.raddr1 := io.readPorts(1).addr 119 regfile.io.raddr2 := io.readPorts(2).addr 120 regfile.io.raddr3 := io.readPorts(3).addr 121 regfile.io.raddr4 := io.readPorts(4).addr 122 regfile.io.raddr5 := io.readPorts(5).addr 123 regfile.io.raddr6 := io.readPorts(6).addr 124 regfile.io.raddr7 := io.readPorts(7).addr 125 regfile.io.raddr8 := io.readPorts(8).addr 126 regfile.io.raddr9 := io.readPorts(9).addr 127 regfile.io.raddr10 := io.readPorts(10).addr 128 regfile.io.raddr11 := io.readPorts(11).addr 129 regfile.io.raddr12 := io.readPorts(12).addr 130 regfile.io.raddr13 := io.readPorts(13).addr 131 regfile.io.raddr14 := DontCare //io.readPorts(14).addr 132 regfile.io.raddr15 := DontCare //io.readPorts(15).addr 133 134 io.readPorts(0).data := regfile.io.rdata0 135 io.readPorts(1).data := regfile.io.rdata1 136 io.readPorts(2).data := regfile.io.rdata2 137 io.readPorts(3).data := regfile.io.rdata3 138 io.readPorts(4).data := regfile.io.rdata4 139 io.readPorts(5).data := regfile.io.rdata5 140 io.readPorts(6).data := regfile.io.rdata6 141 io.readPorts(7).data := regfile.io.rdata7 142 io.readPorts(8).data := regfile.io.rdata8 143 io.readPorts(9).data := regfile.io.rdata9 144 io.readPorts(10).data := regfile.io.rdata10 145 io.readPorts(11).data := regfile.io.rdata11 146 io.readPorts(12).data := regfile.io.rdata12 147 io.readPorts(13).data := regfile.io.rdata13 148 } 149 150} 151 152class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource { 153 154 val io = IO(new Bundle{ 155 val clk = Input(Clock()) 156 val gpr = Input(Bool()) 157 158 // write 159 val wen0, wen1, wen2, wen3, wen4, wen5, wen6, wen7, wen8, wen9 = Input(Bool()) 160 val waddr0, waddr1, waddr2, waddr3, waddr4, waddr5, waddr6, waddr7, waddr8, waddr9 = Input(UInt(8.W)) 161 val wdata0, wdata1, wdata2, wdata3, wdata4, wdata5, wdata6, wdata7, wdata8, wdata9 = Input(UInt(64.W)) 162 163 // read 164 val raddr0, raddr1, raddr2, raddr3, raddr4, raddr5, raddr6, raddr7 = Input(UInt(8.W)) 165 val raddr8, raddr9, raddr10, raddr11, raddr12, raddr13, raddr14, raddr15 = Input(UInt(8.W)) 166 val rdata0, rdata1, rdata2, rdata3, rdata4, rdata5, rdata6, rdata7 = Output(UInt(64.W)) 167 val rdata8, rdata9, rdata10, rdata11, rdata12, rdata13, rdata14, rdata15 = Output(UInt(64.W)) 168 }) 169 170 val vsrc = "/vsrc/regfile_160x64_10w16r_sim.v" 171 println(s"Regfile: Using verilog source at: $vsrc") 172 setResource(vsrc) 173 174} 175 176