1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.regfile 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import xiangshan._ 24 25class RfReadPort(len: Int)(implicit p: Parameters) extends XSBundle { 26 val addr = Input(UInt(PhyRegIdxWidth.W)) 27 val data = Output(UInt(len.W)) 28 override def cloneType: RfReadPort.this.type = 29 new RfReadPort(len).asInstanceOf[this.type] 30} 31 32class RfWritePort(len: Int)(implicit p: Parameters) extends XSBundle { 33 val wen = Input(Bool()) 34 val addr = Input(UInt(PhyRegIdxWidth.W)) 35 val data = Input(UInt(len.W)) 36 override def cloneType: RfWritePort.this.type = 37 new RfWritePort(len).asInstanceOf[this.type] 38} 39 40class Regfile 41( 42 numReadPorts: Int, 43 numWirtePorts: Int, 44 hasZero: Boolean, 45 len: Int 46)(implicit p: Parameters) extends XSModule { 47 val io = IO(new Bundle() { 48 val readPorts = Vec(numReadPorts, new RfReadPort(len)) 49 val writePorts = Vec(numWirtePorts, new RfWritePort(len)) 50 val debug_rports = Vec(32, new RfReadPort(len)) 51 }) 52 53 println("Regfile: size:" + NRPhyRegs + " read: " + numReadPorts + " write: " + numWirtePorts) 54 55 val useBlackBox = false 56 if (!useBlackBox) { 57 val mem = Reg(Vec(NRPhyRegs, UInt(len.W))) 58 for (r <- io.readPorts) { 59 val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr) 60 r.data := RegNext(rdata) 61 } 62 for (w <- io.writePorts) { 63 when(w.wen) { 64 mem(w.addr) := w.data 65 } 66 } 67 68 for (rport <- io.debug_rports) { 69 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 70 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 71 } 72 when (reset.asBool()) { 73 mem.map(_ := 0.U) 74 } 75 } else { 76 77 val regfile = Module(new regfile_160x64_10w16r_sim) 78 79 regfile.clk := this.clock 80 regfile.gpr := hasZero.B 81 82 regfile.wen0 := io.writePorts(0).wen 83 regfile.waddr0 := io.writePorts(0).addr 84 regfile.wdata0 := io.writePorts(0).data 85 86 regfile.wen1 := io.writePorts(1).wen 87 regfile.waddr1 := io.writePorts(1).addr 88 regfile.wdata1 := io.writePorts(1).data 89 90 regfile.wen2 := io.writePorts(2).wen 91 regfile.waddr2 := io.writePorts(2).addr 92 regfile.wdata2 := io.writePorts(2).data 93 94 regfile.wen3 := io.writePorts(3).wen 95 regfile.waddr3 := io.writePorts(3).addr 96 regfile.wdata3 := io.writePorts(3).data 97 98 regfile.wen4 := io.writePorts(4).wen 99 regfile.waddr4 := io.writePorts(4).addr 100 regfile.wdata4 := io.writePorts(4).data 101 102 regfile.wen5 := io.writePorts(5).wen 103 regfile.waddr5 := io.writePorts(5).addr 104 regfile.wdata5 := io.writePorts(5).data 105 106 regfile.wen6 := io.writePorts(6).wen 107 regfile.waddr6 := io.writePorts(6).addr 108 regfile.wdata6 := io.writePorts(6).data 109 110 regfile.wen7 := io.writePorts(7).wen 111 regfile.waddr7 := io.writePorts(7).addr 112 regfile.wdata7 := io.writePorts(7).data 113 114 regfile.wen8 := false.B //io.writePorts(8).wen 115 regfile.waddr8 := DontCare //io.writePorts(8).addr 116 regfile.wdata8 := DontCare //io.writePorts(8).data 117 118 regfile.wen9 := false.B //io.writePorts(9).wen 119 regfile.waddr9 := DontCare //io.writePorts(9).addr 120 regfile.wdata9 := DontCare //io.writePorts(9).data 121 122 123 regfile.raddr0 := io.readPorts(0).addr 124 regfile.raddr1 := io.readPorts(1).addr 125 regfile.raddr2 := io.readPorts(2).addr 126 regfile.raddr3 := io.readPorts(3).addr 127 regfile.raddr4 := io.readPorts(4).addr 128 regfile.raddr5 := io.readPorts(5).addr 129 regfile.raddr6 := io.readPorts(6).addr 130 regfile.raddr7 := io.readPorts(7).addr 131 regfile.raddr8 := io.readPorts(8).addr 132 regfile.raddr9 := io.readPorts(9).addr 133 regfile.raddr10 := io.readPorts(10).addr 134 regfile.raddr11 := io.readPorts(11).addr 135 regfile.raddr12 := io.readPorts(12).addr 136 regfile.raddr13 := io.readPorts(13).addr 137 regfile.raddr14 := DontCare //io.readPorts(14).addr 138 regfile.raddr15 := DontCare //io.readPorts(15).addr 139 140 io.readPorts(0).data := regfile.rdata0 141 io.readPorts(1).data := regfile.rdata1 142 io.readPorts(2).data := regfile.rdata2 143 io.readPorts(3).data := regfile.rdata3 144 io.readPorts(4).data := regfile.rdata4 145 io.readPorts(5).data := regfile.rdata5 146 io.readPorts(6).data := regfile.rdata6 147 io.readPorts(7).data := regfile.rdata7 148 io.readPorts(8).data := regfile.rdata8 149 io.readPorts(9).data := regfile.rdata9 150 io.readPorts(10).data := regfile.rdata10 151 io.readPorts(11).data := regfile.rdata11 152 io.readPorts(12).data := regfile.rdata12 153 io.readPorts(13).data := regfile.rdata13 154 155 io.debug_rports := DontCare 156 } 157 158} 159 160class regfile_160x64_10w16r_sim extends ExtModule with HasExtModuleResource { 161 162 163 val clk = IO(Input(Clock())) 164 val gpr = IO(Input(Bool())) 165 166 // write 167 val wen0, wen1, wen2, wen3, wen4, wen5, wen6, wen7, wen8, wen9 = IO(Input(Bool())) 168 val waddr0, waddr1, waddr2, waddr3, waddr4, waddr5, waddr6, waddr7, waddr8, waddr9 = IO(Input(UInt(8.W))) 169 val wdata0, wdata1, wdata2, wdata3, wdata4, wdata5, wdata6, wdata7, wdata8, wdata9 = IO(Input(UInt(64.W))) 170 171 // read 172 val raddr0, raddr1, raddr2, raddr3, raddr4, raddr5, raddr6, raddr7 = IO(Input(UInt(8.W))) 173 val raddr8, raddr9, raddr10, raddr11, raddr12, raddr13, raddr14, raddr15 = IO(Input(UInt(8.W))) 174 val rdata0, rdata1, rdata2, rdata3, rdata4, rdata5, rdata6, rdata7 = IO(Output(UInt(64.W))) 175 val rdata8, rdata9, rdata10, rdata11, rdata12, rdata13, rdata14, rdata15 = IO(Output(UInt(64.W))) 176 177 val vsrc = "/vsrc/regfile_160x64_10w16r_sim.v" 178 println(s"Regfile: Using verilog source at: $vsrc") 179 addResource(vsrc) 180 181} 182 183