1package xiangshan.backend.regfile 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6 7object hartIdRFInt extends (() => Int) { 8 var x = 0 9 def apply(): Int = { 10 x = x + 1 11 x-1 12 } 13} 14 15object hartIdRFFp extends (() => Int) { 16 var x = 0 17 def apply(): Int = { 18 x = x + 1 19 x-1 20 } 21} 22 23class RfReadPort(len: Int) extends XSBundle { 24 val addr = Input(UInt(PhyRegIdxWidth.W)) 25 val data = Output(UInt(len.W)) 26 override def cloneType: RfReadPort.this.type = 27 new RfReadPort(len).asInstanceOf[this.type] 28} 29 30class RfWritePort(len: Int) extends XSBundle { 31 val wen = Input(Bool()) 32 val addr = Input(UInt(PhyRegIdxWidth.W)) 33 val data = Input(UInt(len.W)) 34 override def cloneType: RfWritePort.this.type = 35 new RfWritePort(len).asInstanceOf[this.type] 36} 37 38class Regfile 39( 40 numReadPorts: Int, 41 numWirtePorts: Int, 42 hasZero: Boolean, 43 len: Int 44) extends XSModule { 45 val io = IO(new Bundle() { 46 val readPorts = Vec(numReadPorts, new RfReadPort(len)) 47 val writePorts = Vec(numWirtePorts, new RfWritePort(len)) 48 }) 49 50 val useBlackBox = false 51 if (!useBlackBox) { 52 val mem = Reg(Vec(NRPhyRegs, UInt(len.W))) 53 for (r <- io.readPorts) { 54 val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr) 55 r.data := RegNext(rdata) 56 } 57 for (w <- io.writePorts) { 58 when(w.wen) { 59 mem(w.addr) := w.data 60 } 61 } 62 63 if (!env.FPGAPlatform) { 64 val id = if (hasZero) hartIdRFInt() else hartIdRFFp() 65 val debugArchRat = WireInit(VecInit(Seq.fill(32)(0.U(PhyRegIdxWidth.W)))) 66 ExcitingUtils.addSink( 67 debugArchRat, 68 if(hasZero) s"DEBUG_INI_ARCH_RAT$id" else s"DEBUG_FP_ARCH_RAT$id", 69 ExcitingUtils.Debug 70 ) 71 72 val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map( 73 x => if(hasZero){ 74 if(x._2 == 0) 0.U else mem(x._1) 75 } else { 76 ieee(mem(x._1)) 77 } 78 ))) 79 ExcitingUtils.addSource( 80 debugArchReg, 81 if(hasZero) s"DEBUG_INT_ARCH_REG$id" else s"DEBUG_FP_ARCH_REG$id", 82 ExcitingUtils.Debug 83 ) 84 } 85 } else { 86 87 val regfile = Module(new regfile_160x64_10w16r_sim) 88 89 regfile.io.clk := this.clock 90 regfile.io.gpr := hasZero.B 91 92 regfile.io.wen0 := io.writePorts(0).wen 93 regfile.io.waddr0 := io.writePorts(0).addr 94 regfile.io.wdata0 := io.writePorts(0).data 95 96 regfile.io.wen1 := io.writePorts(1).wen 97 regfile.io.waddr1 := io.writePorts(1).addr 98 regfile.io.wdata1 := io.writePorts(1).data 99 100 regfile.io.wen2 := io.writePorts(2).wen 101 regfile.io.waddr2 := io.writePorts(2).addr 102 regfile.io.wdata2 := io.writePorts(2).data 103 104 regfile.io.wen3 := io.writePorts(3).wen 105 regfile.io.waddr3 := io.writePorts(3).addr 106 regfile.io.wdata3 := io.writePorts(3).data 107 108 regfile.io.wen4 := io.writePorts(4).wen 109 regfile.io.waddr4 := io.writePorts(4).addr 110 regfile.io.wdata4 := io.writePorts(4).data 111 112 regfile.io.wen5 := io.writePorts(5).wen 113 regfile.io.waddr5 := io.writePorts(5).addr 114 regfile.io.wdata5 := io.writePorts(5).data 115 116 regfile.io.wen6 := io.writePorts(6).wen 117 regfile.io.waddr6 := io.writePorts(6).addr 118 regfile.io.wdata6 := io.writePorts(6).data 119 120 regfile.io.wen7 := io.writePorts(7).wen 121 regfile.io.waddr7 := io.writePorts(7).addr 122 regfile.io.wdata7 := io.writePorts(7).data 123 124 regfile.io.wen8 := false.B //io.writePorts(8).wen 125 regfile.io.waddr8 := DontCare //io.writePorts(8).addr 126 regfile.io.wdata8 := DontCare //io.writePorts(8).data 127 128 regfile.io.wen9 := false.B //io.writePorts(9).wen 129 regfile.io.waddr9 := DontCare //io.writePorts(9).addr 130 regfile.io.wdata9 := DontCare //io.writePorts(9).data 131 132 133 regfile.io.raddr0 := io.readPorts(0).addr 134 regfile.io.raddr1 := io.readPorts(1).addr 135 regfile.io.raddr2 := io.readPorts(2).addr 136 regfile.io.raddr3 := io.readPorts(3).addr 137 regfile.io.raddr4 := io.readPorts(4).addr 138 regfile.io.raddr5 := io.readPorts(5).addr 139 regfile.io.raddr6 := io.readPorts(6).addr 140 regfile.io.raddr7 := io.readPorts(7).addr 141 regfile.io.raddr8 := io.readPorts(8).addr 142 regfile.io.raddr9 := io.readPorts(9).addr 143 regfile.io.raddr10 := io.readPorts(10).addr 144 regfile.io.raddr11 := io.readPorts(11).addr 145 regfile.io.raddr12 := io.readPorts(12).addr 146 regfile.io.raddr13 := io.readPorts(13).addr 147 regfile.io.raddr14 := DontCare //io.readPorts(14).addr 148 regfile.io.raddr15 := DontCare //io.readPorts(15).addr 149 150 io.readPorts(0).data := regfile.io.rdata0 151 io.readPorts(1).data := regfile.io.rdata1 152 io.readPorts(2).data := regfile.io.rdata2 153 io.readPorts(3).data := regfile.io.rdata3 154 io.readPorts(4).data := regfile.io.rdata4 155 io.readPorts(5).data := regfile.io.rdata5 156 io.readPorts(6).data := regfile.io.rdata6 157 io.readPorts(7).data := regfile.io.rdata7 158 io.readPorts(8).data := regfile.io.rdata8 159 io.readPorts(9).data := regfile.io.rdata9 160 io.readPorts(10).data := regfile.io.rdata10 161 io.readPorts(11).data := regfile.io.rdata11 162 io.readPorts(12).data := regfile.io.rdata12 163 io.readPorts(13).data := regfile.io.rdata13 164 } 165 166} 167 168class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource { 169 170 val io = IO(new Bundle{ 171 val clk = Input(Clock()) 172 val gpr = Input(Bool()) 173 174 // write 175 val wen0, wen1, wen2, wen3, wen4, wen5, wen6, wen7, wen8, wen9 = Input(Bool()) 176 val waddr0, waddr1, waddr2, waddr3, waddr4, waddr5, waddr6, waddr7, waddr8, waddr9 = Input(UInt(8.W)) 177 val wdata0, wdata1, wdata2, wdata3, wdata4, wdata5, wdata6, wdata7, wdata8, wdata9 = Input(UInt(64.W)) 178 179 // read 180 val raddr0, raddr1, raddr2, raddr3, raddr4, raddr5, raddr6, raddr7 = Input(UInt(8.W)) 181 val raddr8, raddr9, raddr10, raddr11, raddr12, raddr13, raddr14, raddr15 = Input(UInt(8.W)) 182 val rdata0, rdata1, rdata2, rdata3, rdata4, rdata5, rdata6, rdata7 = Output(UInt(64.W)) 183 val rdata8, rdata9, rdata10, rdata11, rdata12, rdata13, rdata14, rdata15 = Output(UInt(64.W)) 184 }) 185 186 val vsrc = "/vsrc/regfile_160x64_10w16r_sim.v" 187 println(s"Regfile: Using verilog source at: $vsrc") 188 setResource(vsrc) 189 190} 191 192