xref: /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala (revision 3802dba502b91d813c1e563035b876c4e6288166) 
1package xiangshan.backend.regfile
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6
7object hartIdRFInt extends (() => Int) {
8  var x = 0
9  def apply(): Int = {
10    x = x + 1
11    x-1
12  }
13}
14
15object hartIdRFFp extends (() => Int) {
16  var x = 0
17  def apply(): Int = {
18    x = x + 1
19    x-1
20  }
21}
22
23class RfReadPort(len: Int) extends XSBundle {
24  val addr = Input(UInt(PhyRegIdxWidth.W))
25  val data = Output(UInt(len.W))
26  override def cloneType: RfReadPort.this.type =
27    new RfReadPort(len).asInstanceOf[this.type]
28}
29
30class RfWritePort(len: Int) extends XSBundle {
31  val wen = Input(Bool())
32  val addr = Input(UInt(PhyRegIdxWidth.W))
33  val data = Input(UInt(len.W))
34  override def cloneType: RfWritePort.this.type =
35    new RfWritePort(len).asInstanceOf[this.type]
36}
37
38class Regfile
39(
40  numReadPorts: Int,
41  numWirtePorts: Int,
42  hasZero: Boolean,
43  len: Int
44) extends XSModule {
45  val io = IO(new Bundle() {
46    val readPorts = Vec(numReadPorts, new RfReadPort(len))
47    val writePorts = Vec(numWirtePorts, new RfWritePort(len))
48  })
49
50  val useBlackBox = false
51  if (!useBlackBox) {
52    val mem = Mem(NRPhyRegs, UInt(len.W))
53    for (r <- io.readPorts) {
54      val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr)
55      r.data := RegNext(rdata)
56    }
57    for (w <- io.writePorts) {
58      when(w.wen) {
59        mem(w.addr) := w.data
60      }
61    }
62
63    if (!env.FPGAPlatform) {
64      val debugArchRat = WireInit(VecInit(Seq.fill(32)(0.U(PhyRegIdxWidth.W))))
65      ExcitingUtils.addSink(
66        debugArchRat,
67        if(hasZero) "DEBUG_INI_ARCH_RAT" else "DEBUG_FP_ARCH_RAT",
68        ExcitingUtils.Debug
69      )
70
71      val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map(
72        x => if(hasZero){
73          if(x._2 == 0) 0.U else mem(x._1)
74        } else {
75          ieee(mem(x._1))
76        }
77      )))
78      ExcitingUtils.addSource(
79        debugArchReg,
80        if(hasZero) "DEBUG_INT_ARCH_REG" else "DEBUG_FP_ARCH_REG",
81        ExcitingUtils.Debug
82      )
83    }
84
85    if (env.DualCoreDifftest) {
86      val id = if (hasZero) hartIdRFInt() else hartIdRFFp()
87      val debugArchRat = WireInit(VecInit(Seq.fill(32)(0.U(PhyRegIdxWidth.W))))
88      ExcitingUtils.addSink(
89        debugArchRat,
90        if(hasZero) s"DEBUG_INI_ARCH_RAT$id" else s"DEBUG_FP_ARCH_RAT$id",
91        ExcitingUtils.Debug
92      )
93
94      val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map(
95        x => if(hasZero){
96          if(x._2 == 0) 0.U else mem(x._1)
97        } else {
98          ieee(mem(x._1))
99        }
100      )))
101      ExcitingUtils.addSource(
102        debugArchReg,
103        if(hasZero) s"DEBUG_INT_ARCH_REG$id" else s"DEBUG_FP_ARCH_REG$id",
104        ExcitingUtils.Debug
105      )
106    }
107  } else {
108
109    val regfile = Module(new regfile_160x64_10w16r_sim)
110
111    regfile.io.clk := this.clock
112    regfile.io.gpr := hasZero.B
113
114    regfile.io.wen0   := io.writePorts(0).wen
115    regfile.io.waddr0 := io.writePorts(0).addr
116    regfile.io.wdata0 := io.writePorts(0).data
117
118    regfile.io.wen1   := io.writePorts(1).wen
119    regfile.io.waddr1 := io.writePorts(1).addr
120    regfile.io.wdata1 := io.writePorts(1).data
121
122    regfile.io.wen2   := io.writePorts(2).wen
123    regfile.io.waddr2 := io.writePorts(2).addr
124    regfile.io.wdata2 := io.writePorts(2).data
125
126    regfile.io.wen3   := io.writePorts(3).wen
127    regfile.io.waddr3 := io.writePorts(3).addr
128    regfile.io.wdata3 := io.writePorts(3).data
129
130    regfile.io.wen4   := io.writePorts(4).wen
131    regfile.io.waddr4 := io.writePorts(4).addr
132    regfile.io.wdata4 := io.writePorts(4).data
133
134    regfile.io.wen5   := io.writePorts(5).wen
135    regfile.io.waddr5 := io.writePorts(5).addr
136    regfile.io.wdata5 := io.writePorts(5).data
137
138    regfile.io.wen6   := io.writePorts(6).wen
139    regfile.io.waddr6 := io.writePorts(6).addr
140    regfile.io.wdata6 := io.writePorts(6).data
141
142    regfile.io.wen7   := io.writePorts(7).wen
143    regfile.io.waddr7 := io.writePorts(7).addr
144    regfile.io.wdata7 := io.writePorts(7).data
145
146    regfile.io.wen8   := false.B   //io.writePorts(8).wen
147    regfile.io.waddr8 := DontCare  //io.writePorts(8).addr
148    regfile.io.wdata8 := DontCare  //io.writePorts(8).data
149
150    regfile.io.wen9   := false.B   //io.writePorts(9).wen
151    regfile.io.waddr9 := DontCare  //io.writePorts(9).addr
152    regfile.io.wdata9 := DontCare  //io.writePorts(9).data
153
154
155    regfile.io.raddr0  := io.readPorts(0).addr
156    regfile.io.raddr1  := io.readPorts(1).addr
157    regfile.io.raddr2  := io.readPorts(2).addr
158    regfile.io.raddr3  := io.readPorts(3).addr
159    regfile.io.raddr4  := io.readPorts(4).addr
160    regfile.io.raddr5  := io.readPorts(5).addr
161    regfile.io.raddr6  := io.readPorts(6).addr
162    regfile.io.raddr7  := io.readPorts(7).addr
163    regfile.io.raddr8  := io.readPorts(8).addr
164    regfile.io.raddr9  := io.readPorts(9).addr
165    regfile.io.raddr10 := io.readPorts(10).addr
166    regfile.io.raddr11 := io.readPorts(11).addr
167    regfile.io.raddr12 := io.readPorts(12).addr
168    regfile.io.raddr13 := io.readPorts(13).addr
169    regfile.io.raddr14 := DontCare //io.readPorts(14).addr
170    regfile.io.raddr15 := DontCare //io.readPorts(15).addr
171
172    io.readPorts(0).data := regfile.io.rdata0
173    io.readPorts(1).data := regfile.io.rdata1
174    io.readPorts(2).data := regfile.io.rdata2
175    io.readPorts(3).data := regfile.io.rdata3
176    io.readPorts(4).data := regfile.io.rdata4
177    io.readPorts(5).data := regfile.io.rdata5
178    io.readPorts(6).data := regfile.io.rdata6
179    io.readPorts(7).data := regfile.io.rdata7
180    io.readPorts(8).data := regfile.io.rdata8
181    io.readPorts(9).data := regfile.io.rdata9
182    io.readPorts(10).data := regfile.io.rdata10
183    io.readPorts(11).data := regfile.io.rdata11
184    io.readPorts(12).data := regfile.io.rdata12
185    io.readPorts(13).data := regfile.io.rdata13
186  }
187
188}
189
190class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource {
191
192  val io = IO(new Bundle{
193    val clk = Input(Clock())
194    val gpr = Input(Bool())
195
196    // write
197    val wen0, wen1, wen2, wen3, wen4, wen5, wen6, wen7, wen8, wen9 = Input(Bool())
198    val waddr0, waddr1, waddr2, waddr3, waddr4, waddr5, waddr6, waddr7, waddr8, waddr9 = Input(UInt(8.W))
199    val wdata0, wdata1, wdata2, wdata3, wdata4, wdata5, wdata6, wdata7, wdata8, wdata9 = Input(UInt(64.W))
200
201    // read
202    val raddr0, raddr1, raddr2, raddr3, raddr4, raddr5, raddr6, raddr7 = Input(UInt(8.W))
203    val raddr8, raddr9, raddr10, raddr11, raddr12, raddr13, raddr14, raddr15 = Input(UInt(8.W))
204    val rdata0, rdata1, rdata2, rdata3, rdata4, rdata5, rdata6, rdata7 = Output(UInt(64.W))
205    val rdata8, rdata9, rdata10, rdata11, rdata12, rdata13, rdata14, rdata15 = Output(UInt(64.W))
206  })
207
208  val vsrc = "/vsrc/regfile_160x64_10w16r_sim.v"
209  println(s"Regfile: Using verilog source at: $vsrc")
210  setResource(vsrc)
211
212}
213
214