1/**************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 **************************************************************************************** 16 */ 17 18 19package xiangshan.backend.fu.wrapper 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import freechips.rocketchip.rocket.DecodeLogic 25import utility._ 26import utils.XSError 27import xiangshan.{SelImm, SrcType, UopSplitType, XSCoreParamsKey, XSModule} 28import xiangshan.backend.fu.FuConfig 29import xiangshan.backend.fu.vector.Bundles.VSew 30import xiangshan.backend.fu.vector.utils.VecDataSplitModule 31import xiangshan.backend.fu.vector.{Mgu, Utils, VecPipedFuncUnit, VecSrcTypeModule} 32import xiangshan.SrcType 33import yunsuan.vector.alu.{VAluOpcode, VIAlu} 34import yunsuan.{OpType, VipuType} 35 36import scala.collection.Seq 37 38class VIAluDecodeResultBundle extends Bundle { 39 val opcode = UInt(6.W) 40 val srcType2 = UInt(3.W) 41 val srcType1 = UInt(3.W) 42 val vdType = UInt(3.W) 43} 44 45class VIAluDecoder (implicit p: Parameters) extends XSModule { 46 val io = IO(new Bundle{ 47 val in = Input(new Bundle{ 48 val fuOpType = UInt(8.W) 49 val sew = UInt(2.W) 50 }) 51 val out = Output(new VIAluDecodeResultBundle) 52 }) 53 54 // u 00 s 01 f 10 mask 1111 55 // Cat(1(1111),1(s)/0(u), 1(add1)/0(add0)) 56 val uSew = BitPat("b000") 57 val uSew2 = BitPat("b001") 58 val sSew = BitPat("b010") 59 val sSew2 = BitPat("b011") 60 val mask = BitPat("b100".U(3.W)) 61 val default = List(BitPat("b000000"),BitPat("b000"),BitPat("b000"),BitPat("b000")) 62 val decodeTable : Array[(BitPat, List[BitPat])] = Array( 63 BitPat(VipuType.vredsum_vs) -> List(BitPat(VAluOpcode.vredsum), uSew, uSew, uSew), 64 BitPat(VipuType.vredmaxu_vs) -> List(BitPat(VAluOpcode.vredmax), uSew, uSew, uSew), 65 BitPat(VipuType.vredmax_vs) -> List(BitPat(VAluOpcode.vredmax), sSew, sSew, sSew), 66 BitPat(VipuType.vredminu_vs) -> List(BitPat(VAluOpcode.vredmin), uSew, uSew, uSew), 67 BitPat(VipuType.vredmin_vs) -> List(BitPat(VAluOpcode.vredmin), sSew, sSew, sSew), 68 BitPat(VipuType.vredand_vs) -> List(BitPat(VAluOpcode.vredand), uSew, uSew, uSew), 69 BitPat(VipuType.vredor_vs) -> List(BitPat(VAluOpcode.vredor), uSew, uSew, uSew), 70 BitPat(VipuType.vredxor_vs) -> List(BitPat(VAluOpcode.vredxor), uSew, uSew, uSew), 71 72 BitPat(VipuType.vwredsumu_vs) -> List(BitPat(VAluOpcode.vredsum), uSew, uSew, uSew2), 73 BitPat(VipuType.vwredsum_vs) -> List(BitPat(VAluOpcode.vredsum), sSew, sSew, sSew2), 74 75 BitPat(VipuType.vcpop_m) -> List(BitPat(VAluOpcode.vcpop), mask, mask, uSew), 76 BitPat(VipuType.vfirst_m) -> List(BitPat(VAluOpcode.vfirst), mask, mask, uSew), 77 BitPat(VipuType.vmsbf_m) -> List(BitPat(VAluOpcode.vmsbf), mask, mask, mask), 78 BitPat(VipuType.vmsif_m) -> List(BitPat(VAluOpcode.vmsif), mask, mask, mask), 79 BitPat(VipuType.vmsof_m) -> List(BitPat(VAluOpcode.vmsof), mask, mask, mask), 80 81 BitPat(VipuType.viota_m) -> List(BitPat(VAluOpcode.viota), uSew, uSew, uSew), 82 BitPat(VipuType.vid_v) -> List(BitPat(VAluOpcode.vid), uSew, uSew, uSew), 83 BitPat(VipuType.vmv_x_s) -> List(BitPat(VAluOpcode.vmvxs), uSew, uSew, uSew) 84 ) 85 val decoder = DecodeLogic(io.in.fuOpType, default, decodeTable) 86 val outsig = Seq(io.out.opcode, io.out.srcType2, io.out.srcType1, io.out.vdType) 87 outsig.zip(decoder).foreach({case (s, d) => s := d}) 88} 89 90class VIPU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 91 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VipuType.dummy, "VIPU OpType not supported") 92 93 // params alias 94 private val dataWidth = cfg.destDataBits 95 private val dataWidthOfDataModule = 64 96 private val numVecModule = dataWidth / dataWidthOfDataModule 97 private val needClearVs1 = (VipuType.vcpop_m === io.in.bits.ctrl.fuOpType && vuopIdx === 0.U) || 98 (VipuType.viota_m === io.in.bits.ctrl.fuOpType && vuopIdx(log2Up(MaxUopSize)-1,1) === 0.U) || 99 (VipuType.vid_v === io.in.bits.ctrl.fuOpType && vuopIdx(log2Up(MaxUopSize)-1,1) === 0.U) // dirty code TODO: inset into IAlu 100 private val lmul = MuxLookup(vlmul, 1.U(4.W))(Array( 101 "b001".U -> 2.U, 102 "b010".U -> 4.U, 103 "b011".U -> 8.U 104 )) 105 private val needShiftVs1 = (VipuType.vwredsumu_vs === io.in.bits.ctrl.fuOpType || VipuType.vwredsum_vs === io.in.bits.ctrl.fuOpType) && vuopIdx < lmul 106 107 // modules 108 private val decoder = Module(new VIAluDecoder) 109 private val vialu = Module(new VIAlu) 110 111 /** 112 * [[decoder]]'s in connection 113 */ 114 decoder.io.in.fuOpType := fuOpType 115 decoder.io.in.sew := vsew(1,0) 116 117 val typeop2 = decoder.io.out.srcType2 118 val typeop1 = decoder.io.out.srcType1 119 val typevd = decoder.io.out.vdType 120 val sew = decoder.io.in.sew 121 122 val srcTypeVs2 = Cat(0.U | typeop2(2) , typeop2(1) | typeop2(2) , Fill(2,typeop2(2)) | (sew + typeop2(0)) ) 123 val srcTypeVs1 = Cat(0.U | typeop1(2) , typeop1(1) | typeop1(2) , Fill(2,typeop1(2)) | (sew + typeop1(0)) ) 124 val vdType = Cat(0.U | typevd(2) , typevd(1) | typevd(2) , Fill(2,typevd(2)) | (sew + typevd(0))) 125 /** 126 * [[vialu]]'s in connection 127 */ 128 vialu.io match { 129 case subIO => 130 subIO.in.valid := io.in.valid 131 subIO.in.bits.opcode.op := decoder.io.out.opcode 132 subIO.in.bits.info.vm := vm 133 subIO.in.bits.info.ma := vma 134 subIO.in.bits.info.ta := vta 135 subIO.in.bits.info.vlmul := vlmul 136 subIO.in.bits.info.vl := srcVConfig.vl 137 subIO.in.bits.info.vstart := vstart 138 subIO.in.bits.info.uopIdx := vuopIdx 139 subIO.in.bits.info.vxrm := vxrm 140 subIO.in.bits.srcType(0) := srcTypeVs2 141 subIO.in.bits.srcType(1) := srcTypeVs1 142 subIO.in.bits.vdType := vdType 143 subIO.in.bits.vs1 := Mux1H(Seq(needClearVs1 -> 0.U, 144 needShiftVs1 -> ZeroExt(vs1(127,64), 128), 145 ((!needClearVs1) && (!needShiftVs1)) -> vs1)) 146 subIO.in.bits.vs2 := vs2 147 subIO.in.bits.old_vd := oldVd 148 subIO.in.bits.mask := srcMask 149 } 150 151 io.out.bits.res.data := vialu.io.out.bits.vd 152} 153