1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, VecPipedFuncUnit} 11import xiangshan.ExceptionNO 12import yunsuan.VfpuType 13import yunsuan.VfmaType 14import yunsuan.vector.VectorFloatFMA 15 16class VFMA(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 17 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 18 19 // params alias 20 private val dataWidth = cfg.dataBits 21 private val dataWidthOfDataModule = 64 22 private val numVecModule = dataWidth / dataWidthOfDataModule 23 24 // io alias 25 private val opcode = fuOpType(3,0) 26 private val resWiden = fuOpType(4) 27 28 // modules 29 private val vfmas = Seq.fill(numVecModule)(Module(new VectorFloatFMA)) 30 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val mgu = Module(new Mgu(dataWidth)) 34 35 /** 36 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 37 */ 38 vs2Split.io.inVecData := vs2 39 vs1Split.io.inVecData := vs1 40 oldVdSplit.io.inVecData := oldVd 41 42 /** 43 * [[vfmas]]'s in connection 44 */ 45 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 46 // Vec( 47 // Cat(vs2(95,64), vs2(31,0)), 48 // Cat(vs2(127,96), vs2(63,32)), 49 // ) 50 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 51 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 52 private val resultData = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W))) 53 private val fflagsData = Wire(Vec(numVecModule, UInt(20.W))) 54 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule, Bool())) 55 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule, Bool())) 56 val fp_cIsFpCanonicalNAN = Wire(Vec(numVecModule, Bool())) 57 vfmas.zipWithIndex.foreach { 58 case (mod, i) => 59 mod.io.fire := io.in.valid 60 mod.io.fp_a := vs2Split.io.outVec64b(i) 61 mod.io.fp_b := vs1Split.io.outVec64b(i) 62 mod.io.fp_c := oldVdSplit.io.outVec64b(i) 63 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 64 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 65 mod.io.frs1 := 0.U // already vf -> vv 66 mod.io.is_frs1 := false.B // already vf -> vv 67 mod.io.uop_idx := vuopIdx(0) 68 mod.io.is_vec := true.B // Todo 69 mod.io.round_mode := rm 70 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 71 mod.io.res_widening := resWiden 72 mod.io.op_code := opcode 73 resultData(i) := mod.io.fp_result 74 fflagsData(i) := mod.io.fflags 75 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 76 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 77 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 78 ) 79 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 80 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 81 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 82 ) 83 fp_cIsFpCanonicalNAN(i) := !(opcode === VfmaType.vfmul) & vecCtrl.fpu.isFpToVecInst & ( 84 ((vsew === VSew.e32) & (!oldVdSplit.io.outVec64b(i).head(32).andR)) | 85 ((vsew === VSew.e16) & (!oldVdSplit.io.outVec64b(i).head(48).andR)) 86 ) 87 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 88 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 89 mod.io.fp_cIsFpCanonicalNAN := fp_cIsFpCanonicalNAN(i) 90 } 91 92 val outFuOpType = outCtrl.fuOpType 93 val outWiden = outCtrl.fuOpType(4) 94 val outEew = Mux(outWiden, outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 95 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 96 val vlMax = ((VLEN / 8).U >> outEew).asUInt 97 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1, 0)).asUInt + 1.U, outVecCtrl.vlmul(1, 0)) 98 val outVlFix = Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) 99 val vlMaxAllUop = Wire(outVl.cloneType) 100 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 101 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 102 val vlSetThisUop = Mux(outVlFix > outVuopidx * vlMaxThisUop, outVlFix - outVuopidx * vlMaxThisUop, 0.U) 103 val vlThisUop = Wire(UInt(3.W)) 104 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 105 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 106 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 107 108 private val needNoMask = outVecCtrl.fpu.isFpToVecInst 109 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 110 val allFFlagsEn = Wire(Vec(4 * numVecModule, Bool())) 111 val outSrcMaskRShift = Wire(UInt((4 * numVecModule).W)) 112 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2, 0) * vlMax))(4 * numVecModule - 1, 0) 113 val f16FFlagsEn = outSrcMaskRShift 114 val f32FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 115 for (i <- 0 until numVecModule) { 116 f32FFlagsEn(i) := Cat(Fill(2, 1.U), outSrcMaskRShift(2 * i + 1, 2 * i)) 117 } 118 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 119 for (i <- 0 until numVecModule) { 120 f64FFlagsEn(i) := Cat(Fill(3, 1.U), outSrcMaskRShift(i)) 121 } 122 val fflagsEn = Mux1H( 123 Seq( 124 (outEew === 1.U) -> f16FFlagsEn.asUInt, 125 (outEew === 2.U) -> f32FFlagsEn.asUInt, 126 (outEew === 3.U) -> f64FFlagsEn.asUInt 127 ) 128 ) 129 allFFlagsEn := (fflagsEn & vlMaskRShift).asTypeOf(allFFlagsEn) 130 131 val allFFlags = fflagsData.asTypeOf(Vec(4 * numVecModule, UInt(5.W))) 132 val outFFlags = allFFlagsEn.zip(allFFlags).map { 133 case (en, fflags) => Mux(en, fflags, 0.U(5.W)) 134 }.reduce(_ | _) 135 io.out.bits.res.fflags.get := outFFlags 136 137 val resultDataUInt = resultData.asUInt 138 mgu.io.in.vd := resultDataUInt 139 mgu.io.in.oldVd := outOldVd 140 mgu.io.in.mask := maskToMgu 141 mgu.io.in.info.ta := outVecCtrl.vta 142 mgu.io.in.info.ma := outVecCtrl.vma 143 mgu.io.in.info.vl := Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) 144 mgu.io.in.info.vlmul := outVecCtrl.vlmul 145 mgu.io.in.info.valid := io.out.valid 146 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 147 mgu.io.in.info.eew := outEew 148 mgu.io.in.info.vsew := outVecCtrl.vsew 149 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 150 mgu.io.in.info.narrow := outVecCtrl.isNarrow 151 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 152 mgu.io.in.isIndexedVls := false.B 153 io.out.bits.res.data := mgu.io.out.vd 154 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 155} 156