1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.{VLmul, VSew, ma} 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Mgtu, VecInfo, VecPipedFuncUnit} 11import xiangshan.ExceptionNO 12import yunsuan.{VfaluType, VfpuType} 13import yunsuan.vector.VectorFloatAdder 14import xiangshan.backend.fu.vector.Bundles.VConfig 15 16class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 17 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 18 19 // params alias 20 private val dataWidth = cfg.dataBits 21 private val dataWidthOfDataModule = 64 22 private val numVecModule = dataWidth / dataWidthOfDataModule 23 24 // io alias 25 private val opcode = fuOpType(4,0) 26 private val resWiden = fuOpType(5) 27 private val opbWiden = fuOpType(6) 28 29 // modules 30 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 31 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 34 private val mgu = Module(new Mgu(dataWidth)) 35 private val mgtu = Module(new Mgtu(dataWidth)) 36 37 /** 38 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 39 */ 40 vs2Split.io.inVecData := vs2 41 vs1Split.io.inVecData := vs1 42 oldVdSplit.io.inVecData := oldVd 43 44 /** 45 * [[vfalus]]'s in connection 46 */ 47 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 48 // Vec( 49 // Cat(vs2(95,64), vs2(31,0)), 50 // Cat(vs2(127,96), vs2(63,32)), 51 // ) 52 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 53 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 54 private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W))) 55 private val fflagsData = Wire(Vec(numVecModule,UInt(20.W))) 56 private val srcMaskRShiftForReduction = Wire(UInt((8 * numVecModule).W)) 57 // for reduction 58 val isFirstGroupUop = vuopIdx === 0.U || 59 (vuopIdx === 1.U && (vlmul === VLmul.m4 || vlmul === VLmul.m8)) || 60 ((vuopIdx === 2.U || vuopIdx === 3.U) && vlmul === VLmul.m8) 61 val maskRshiftWidthForReduction = Wire(UInt(6.W)) 62 maskRshiftWidthForReduction := Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 63 vuopIdx, 64 Mux1H(Seq( 65 (vsew === VSew.e16) -> (vuopIdx(1, 0) << 4), 66 (vsew === VSew.e32) -> (vuopIdx(1, 0) << 3), 67 (vsew === VSew.e64) -> (vuopIdx(1, 0) << 2), 68 )) 69 ) 70 val vlMaskForReduction = (~(Fill(VLEN, 1.U) << vl)).asUInt 71 srcMaskRShiftForReduction := ((srcMask & vlMaskForReduction) >> maskRshiftWidthForReduction)(8 * numVecModule - 1, 0) 72 73 def genMaskForReduction(inmask: UInt, sew: UInt, i: Int): UInt = { 74 val f64MaskNum = dataWidth / 64 * 2 75 val f32MaskNum = dataWidth / 32 * 2 76 val f16MaskNum = dataWidth / 16 * 2 77 val f64Mask = inmask(f64MaskNum - 1, 0) 78 val f32Mask = inmask(f32MaskNum - 1, 0) 79 val f16Mask = inmask(f16MaskNum - 1, 0) 80 // vs2 reordered, so mask use high bits 81 val f64FirstFoldMaskUnorder = Mux1H( 82 Seq( 83 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(0), 0.U(3.W), f64Mask(1)), 84 ) 85 ) 86 val f64FirstFoldMaskOrder = Mux1H( 87 Seq( 88 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(1), 0.U(3.W), f64Mask(0)) 89 ) 90 ) 91 val f32FirstFoldMaskUnorder = Mux1H( 92 Seq( 93 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(1), f32Mask(0), 0.U(2.W), f32Mask(3), f32Mask(2)), 94 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(0), 0.U(3.W), f32Mask(1)), 95 ) 96 ) 97 val f32FirstFoldMaskOrder = Mux1H( 98 Seq( 99 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(3), f32Mask(2), 0.U(2.W), f32Mask(1), f32Mask(0)), 100 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(1), 0.U(3.W), f32Mask(0)), 101 ) 102 ) 103 val f16FirstFoldMaskUnorder = Mux1H( 104 Seq( 105 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 106 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(1), f16Mask(0), 0.U(2.W), f16Mask(3), f16Mask(2)), 107 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(0), 0.U(3.W), f16Mask(1)), 108 ) 109 ) 110 val f16FirstFoldMaskOrder = Mux1H( 111 Seq( 112 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 113 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(3), f16Mask(2), 0.U(2.W), f16Mask(1), f16Mask(0)), 114 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(1), 0.U(3.W), f16Mask(0)), 115 ) 116 ) 117 val f64FoldMask = Mux1H( 118 Seq( 119 vecCtrl.fpu.isFoldTo1_2 -> "b00010001".U, 120 ) 121 ) 122 val f32FoldMask = Mux1H( 123 Seq( 124 vecCtrl.fpu.isFoldTo1_2 -> "b00110011".U, 125 vecCtrl.fpu.isFoldTo1_4 -> "b00010001".U, 126 ) 127 ) 128 val f16FoldMask = Mux1H( 129 Seq( 130 vecCtrl.fpu.isFoldTo1_2 -> "b11111111".U, 131 vecCtrl.fpu.isFoldTo1_4 -> "b00110011".U, 132 vecCtrl.fpu.isFoldTo1_8 -> "b00010001".U, 133 ) 134 ) 135 // low 4 bits for vs2(fp_a), high 4 bits for vs1(fp_b), 136 val isFold = vecCtrl.fpu.isFoldTo1_2 || vecCtrl.fpu.isFoldTo1_4 || vecCtrl.fpu.isFoldTo1_8 137 val f64FirstNotFoldMask = Cat(0.U(3.W), f64Mask(i + 2), 0.U(3.W), f64Mask(i)) 138 val f32FirstNotFoldMask = Cat(0.U(2.W), f32Mask(i * 2 + 5, i * 2 + 4), 0.U(2.W), Cat(f32Mask(i * 2 + 1, i * 2))) 139 val f16FirstNotFoldMask = Cat(f16Mask(i * 4 + 11, i * 4 + 8), f16Mask(i * 4 + 3, i * 4)) 140 val f64MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 141 Mux(isFold, f64FirstFoldMaskOrder, f64FirstNotFoldMask), 142 Mux(isFirstGroupUop, 143 Mux(isFold, f64FirstFoldMaskUnorder, f64FirstNotFoldMask), 144 Mux(isFold, f64FoldMask, Fill(8, 1.U)))) 145 val f32MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 146 Mux(isFold, f32FirstFoldMaskOrder, f32FirstNotFoldMask), 147 Mux(isFirstGroupUop, 148 Mux(isFold, f32FirstFoldMaskUnorder, f32FirstNotFoldMask), 149 Mux(isFold, f32FoldMask, Fill(8, 1.U)))) 150 val f16MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 151 Mux(isFold, f16FirstFoldMaskOrder, f16FirstNotFoldMask), 152 Mux(isFirstGroupUop, 153 Mux(isFold, f16FirstFoldMaskUnorder, f16FirstNotFoldMask), 154 Mux(isFold, f16FoldMask, Fill(8, 1.U)))) 155 val outMask = Mux1H( 156 Seq( 157 (sew === 3.U) -> f64MaskI, 158 (sew === 2.U) -> f32MaskI, 159 (sew === 1.U) -> f16MaskI, 160 ) 161 ) 162 Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, outMask(0),outMask) 163 } 164 def genMaskForMerge(inmask:UInt, sew:UInt, i:Int): UInt = { 165 val f64MaskNum = dataWidth / 64 166 val f32MaskNum = dataWidth / 32 167 val f16MaskNum = dataWidth / 16 168 val f64Mask = inmask(f64MaskNum-1,0) 169 val f32Mask = inmask(f32MaskNum-1,0) 170 val f16Mask = inmask(f16MaskNum-1,0) 171 val f64MaskI = Cat(0.U(3.W),f64Mask(i)) 172 val f32MaskI = Cat(0.U(2.W),f32Mask(2*i+1,2*i)) 173 val f16MaskI = f16Mask(4*i+3,4*i) 174 val outMask = Mux1H( 175 Seq( 176 (sew === 3.U) -> f64MaskI, 177 (sew === 2.U) -> f32MaskI, 178 (sew === 1.U) -> f16MaskI, 179 ) 180 ) 181 outMask 182 } 183 val isScalarMove = (fuOpType === VfaluType.vfmv_f_s) || (fuOpType === VfaluType.vfmv_s_f) 184 val srcMaskRShift = Wire(UInt((4 * numVecModule).W)) 185 val maskRshiftWidth = Wire(UInt(6.W)) 186 maskRshiftWidth := Mux1H( 187 Seq( 188 (vsew === VSew.e16) -> (vuopIdx(2,0) << 3), 189 (vsew === VSew.e32) -> (vuopIdx(2,0) << 2), 190 (vsew === VSew.e64) -> (vuopIdx(2,0) << 1), 191 ) 192 ) 193 srcMaskRShift := (srcMask >> maskRshiftWidth)(4 * numVecModule - 1, 0) 194 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 195 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 196 val inIsFold = Wire(UInt(3.W)) 197 inIsFold := Cat(vecCtrl.fpu.isFoldTo1_8, vecCtrl.fpu.isFoldTo1_4, vecCtrl.fpu.isFoldTo1_2) 198 vfalus.zipWithIndex.foreach { 199 case (mod, i) => 200 mod.io.fire := io.in.valid 201 mod.io.fp_a := vs2Split.io.outVec64b(i) 202 mod.io.fp_b := vs1Split.io.outVec64b(i) 203 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 204 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 205 mod.io.frs1 := 0.U // already vf -> vv 206 mod.io.is_frs1 := false.B // already vf -> vv 207 mod.io.mask := Mux(isScalarMove, !vuopIdx.orR, genMaskForMerge(inmask = srcMaskRShift, sew = vsew, i = i)) 208 mod.io.maskForReduction := genMaskForReduction(inmask = srcMaskRShiftForReduction, sew = vsew, i = i) 209 mod.io.uop_idx := vuopIdx(0) 210 mod.io.is_vec := true.B // Todo 211 mod.io.round_mode := rm 212 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 213 mod.io.opb_widening := opbWiden 214 mod.io.res_widening := resWiden 215 mod.io.op_code := opcode 216 mod.io.is_vfwredosum := fuOpType === VfaluType.vfwredosum 217 mod.io.is_fold := inIsFold 218 mod.io.vs2_fold := vs2 // for better timing 219 resultData(i) := mod.io.fp_result 220 fflagsData(i) := mod.io.fflags 221 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 222 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 223 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 224 ) 225 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 226 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 227 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 228 ) 229 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 230 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 231 } 232 val resultDataUInt = resultData.asUInt 233 val cmpResultWidth = dataWidth / 16 234 val cmpResult = Wire(Vec(cmpResultWidth, Bool())) 235 for (i <- 0 until cmpResultWidth) { 236 if(i == 0) { 237 cmpResult(i) := resultDataUInt(0) 238 } 239 else if(i < dataWidth / 64) { 240 cmpResult(i) := Mux1H( 241 Seq( 242 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i*16), 243 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i*32), 244 (outVecCtrl.vsew === 3.U) -> resultDataUInt(i*64) 245 ) 246 ) 247 } 248 else if(i < dataWidth / 32) { 249 cmpResult(i) := Mux1H( 250 Seq( 251 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i * 16), 252 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i * 32), 253 (outVecCtrl.vsew === 3.U) -> false.B 254 ) 255 ) 256 } 257 else if(i < dataWidth / 16) { 258 cmpResult(i) := Mux(outVecCtrl.vsew === 1.U, resultDataUInt(i*16), false.B) 259 } 260 } 261 val outCtrl_s0 = ctrlVec.head 262 val outVecCtrl_s0 = ctrlVec.head.vpu.get 263 val outEew_s0 = Mux(resWiden, outVecCtrl_s0.vsew + 1.U, outVecCtrl_s0.vsew) 264 val outEew = Mux(RegEnable(resWiden, io.in.fire), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 265 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 266 val vlMax_s0 = ((VLEN/8).U >> outEew_s0).asUInt 267 val vlMax = ((VLEN/8).U >> outEew).asUInt 268 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1,0)).asUInt + 1.U, outVecCtrl.vlmul(1,0)) 269 // vfmv_f_s need vl=1, reduction last uop need vl=1, other uop need vl=vlmax 270 val numOfUopVFRED = { 271 // addTime include add frs1 272 val addTime = MuxLookup(outVecCtrl_s0.vlmul, 1.U(4.W))(Array( 273 VLmul.m2 -> 2.U, 274 VLmul.m4 -> 4.U, 275 VLmul.m8 -> 8.U, 276 )) 277 val foldLastVlmul = MuxLookup(outVecCtrl_s0.vsew, "b000".U)(Array( 278 VSew.e16 -> VLmul.mf8, 279 VSew.e32 -> VLmul.mf4, 280 VSew.e64 -> VLmul.mf2, 281 )) 282 // lmul < 1, foldTime = vlmul - foldFastVlmul 283 // lmul >= 1, foldTime = 0.U - foldFastVlmul 284 val foldTime = Mux(outVecCtrl_s0.vlmul(2), outVecCtrl_s0.vlmul, 0.U) - foldLastVlmul 285 addTime + foldTime 286 } 287 val reductionVl = Mux((outVecCtrl_s0.vuopIdx === numOfUopVFRED - 1.U) || (outCtrl_s0.fuOpType === VfaluType.vfredosum || outCtrl_s0.fuOpType === VfaluType.vfwredosum), 1.U, vlMax_s0) 288 val outIsResuction = outCtrl.fuOpType === VfaluType.vfredusum || 289 outCtrl.fuOpType === VfaluType.vfredmax || 290 outCtrl.fuOpType === VfaluType.vfredmin || 291 outCtrl.fuOpType === VfaluType.vfredosum || 292 outCtrl.fuOpType === VfaluType.vfwredosum 293 val outIsResuction_s0 = outCtrl_s0.fuOpType === VfaluType.vfredusum || 294 outCtrl_s0.fuOpType === VfaluType.vfredmax || 295 outCtrl_s0.fuOpType === VfaluType.vfredmin || 296 outCtrl_s0.fuOpType === VfaluType.vfredosum || 297 outCtrl_s0.fuOpType === VfaluType.vfwredosum 298 val outVConfig_s0 = if(!cfg.vconfigWakeUp) outVecCtrl_s0.vconfig else dataVec.head.getSrcVConfig.asTypeOf(new VConfig) 299 val outVl_s0 = outVConfig_s0.vl 300 val outVlFix_s0 = Mux( 301 outVecCtrl_s0.fpu.isFpToVecInst || (outCtrl_s0.fuOpType === VfaluType.vfmv_f_s), 302 1.U, 303 Mux( 304 outCtrl_s0.fuOpType === VfaluType.vfmv_s_f, 305 outVl_s0.orR, 306 Mux(outIsResuction_s0, reductionVl, outVl_s0) 307 ) 308 ) 309 val outVlFix = RegEnable(outVlFix_s0,io.in.fire) 310 311 val vlMaxAllUop = Wire(outVl.cloneType) 312 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 313 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 314 val vlSetThisUop = Mux(outVlFix > outVuopidx*vlMaxThisUop, outVlFix - outVuopidx*vlMaxThisUop, 0.U) 315 val vlThisUop = Wire(UInt(3.W)) 316 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 317 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 318 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 319 320 private val needNoMask = outCtrl.fuOpType === VfaluType.vfmerge || 321 outCtrl.fuOpType === VfaluType.vfmv_s_f || 322 outIsResuction || 323 outVecCtrl.fpu.isFpToVecInst 324 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 325 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 326 val outSrcMaskRShift = Wire(UInt((4*numVecModule).W)) 327 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2,0) * vlMax))(4*numVecModule-1,0) 328 val f16FFlagsEn = outSrcMaskRShift 329 val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W))) 330 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 331 val f16VlMaskEn = vlMaskRShift 332 val f32VlMaskEn = Wire(Vec(numVecModule, UInt(4.W))) 333 val f64VlMaskEn = Wire(Vec(numVecModule, UInt(4.W))) 334 for (i <- 0 until numVecModule){ 335 f32FFlagsEn(i) := Cat(Fill(2, 0.U), outSrcMaskRShift(2*i+1,2*i)) 336 f64FFlagsEn(i) := Cat(Fill(3, 0.U), outSrcMaskRShift(i)) 337 f32VlMaskEn(i) := Cat(Fill(2, 0.U), vlMaskRShift(2 * i + 1, 2 * i)) 338 f64VlMaskEn(i) := Cat(Fill(3, 0.U), vlMaskRShift(i)) 339 } 340 val fflagsEn= Mux1H( 341 Seq( 342 (outEew === 1.U) -> f16FFlagsEn.asUInt, 343 (outEew === 2.U) -> f32FFlagsEn.asUInt, 344 (outEew === 3.U) -> f64FFlagsEn.asUInt 345 ) 346 ) 347 val vlMaskEn = Mux1H( 348 Seq( 349 (outEew === 1.U) -> f16VlMaskEn.asUInt, 350 (outEew === 2.U) -> f32VlMaskEn.asUInt, 351 (outEew === 3.U) -> f64VlMaskEn.asUInt 352 ) 353 ) 354 allFFlagsEn := Mux(outIsResuction, Fill(4*numVecModule, 1.U), (fflagsEn & vlMaskEn)).asTypeOf(allFFlagsEn) 355 356 val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W))) 357 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 358 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 359 }.reduce(_ | _) 360 io.out.bits.res.fflags.get := outFFlags 361 362 363 val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) 364 val cmpResultOldVdRshiftWidth = Wire(UInt(6.W)) 365 cmpResultOldVdRshiftWidth := Mux1H( 366 Seq( 367 (outVecCtrl.vsew === VSew.e16) -> (outVecCtrl.vuopIdx(2, 0) << 3), 368 (outVecCtrl.vsew === VSew.e32) -> (outVecCtrl.vuopIdx(2, 0) << 2), 369 (outVecCtrl.vsew === VSew.e64) -> (outVecCtrl.vuopIdx(2, 0) << 1), 370 ) 371 ) 372 cmpResultOldVd := (outOldVd >> cmpResultOldVdRshiftWidth)(4*numVecModule-1,0) 373 val cmpResultForMgu = Wire(Vec(cmpResultWidth, Bool())) 374 private val maxVdIdx = 8 375 private val elementsInOneUop = Mux1H( 376 Seq( 377 (outEew === 1.U) -> (cmpResultWidth).U(4.W), 378 (outEew === 2.U) -> (cmpResultWidth / 2).U(4.W), 379 (outEew === 3.U) -> (cmpResultWidth / 4).U(4.W), 380 ) 381 ) 382 private val vdIdx = outVecCtrl.vuopIdx(2, 0) 383 private val elementsComputed = Mux1H(Seq.tabulate(maxVdIdx)(i => (vdIdx === i.U) -> (elementsInOneUop * i.U))) 384 for (i <- 0 until cmpResultWidth) { 385 val cmpResultWithVmask = Mux(outSrcMaskRShift(i), cmpResult(i), Mux(outVecCtrl.vma, true.B, cmpResultOldVd(i))) 386 cmpResultForMgu(i) := Mux(elementsComputed +& i.U >= outVl, true.B, cmpResultWithVmask) 387 } 388 val outIsFold = outVecCtrl.fpu.isFoldTo1_2 || outVecCtrl.fpu.isFoldTo1_4 || outVecCtrl.fpu.isFoldTo1_8 389 val outOldVdForREDO = Mux1H(Seq( 390 (outVecCtrl.vsew === VSew.e16) -> (outOldVd >> 16), 391 (outVecCtrl.vsew === VSew.e32) -> (outOldVd >> 32), 392 (outVecCtrl.vsew === VSew.e64) -> (outOldVd >> 64), 393 )) 394 val outOldVdForWREDO = Mux( 395 !outIsFold, 396 Mux(outVecCtrl.vsew === VSew.e16, Cat(outOldVd(VLEN-1-16,16), 0.U(32.W)), Cat(outOldVd(VLEN-1-32,32), 0.U(64.W))), 397 Mux(outVecCtrl.vsew === VSew.e16, 398 // Divide vuopIdx by 8 and the remainder is 1 399 Mux(outVecCtrl.vuopIdx(2,0) === 1.U, outOldVd, outOldVd >> 16), 400 // Divide vuopIdx by 4 and the remainder is 1 401 Mux(outVecCtrl.vuopIdx(1,0) === 1.U, outOldVd, outOldVd >> 32) 402 ), 403 ) 404 val outOldVdForRED = Mux(outCtrl.fuOpType === VfaluType.vfredosum, outOldVdForREDO, outOldVdForWREDO) 405 val numOfUopVFREDOSUM = { 406 val uvlMax = MuxLookup(outVecCtrl.vsew, 0.U)(Array( 407 VSew.e16 -> 8.U, 408 VSew.e32 -> 4.U, 409 VSew.e64 -> 2.U, 410 )) 411 val vlMax = Mux(outVecCtrl.vlmul(2), uvlMax >> (-outVecCtrl.vlmul)(1, 0), uvlMax << outVecCtrl.vlmul(1, 0)).asUInt 412 vlMax 413 } 414 val isOutOldVdForREDO = (outCtrl.fuOpType === VfaluType.vfredosum && outIsFold) || outCtrl.fuOpType === VfaluType.vfwredosum 415 val taIsFalseForVFREDO = ((outCtrl.fuOpType === VfaluType.vfredosum) || (outCtrl.fuOpType === VfaluType.vfwredosum)) && (outVecCtrl.vuopIdx =/= numOfUopVFREDOSUM - 1.U) 416 // outVecCtrl.fpu.isFpToVecInst means the instruction is float instruction, not vector float instruction 417 val notUseVl = outVecCtrl.fpu.isFpToVecInst || (outCtrl.fuOpType === VfaluType.vfmv_f_s) 418 val notModifyVd = !notUseVl && (outVl === 0.U) 419 mgu.io.in.vd := Mux(outVecCtrl.isDstMask, Cat(0.U((dataWidth / 16 * 15).W), cmpResultForMgu.asUInt), resultDataUInt) 420 mgu.io.in.oldVd := Mux(isOutOldVdForREDO, outOldVdForRED, outOldVd) 421 mgu.io.in.mask := maskToMgu 422 mgu.io.in.info.ta := Mux(outCtrl.fuOpType === VfaluType.vfmv_f_s, true.B , Mux(taIsFalseForVFREDO, false.B, outVecCtrl.vta)) 423 mgu.io.in.info.ma := Mux(outCtrl.fuOpType === VfaluType.vfmv_s_f, true.B , outVecCtrl.vma) 424 mgu.io.in.info.vl := outVlFix 425 mgu.io.in.info.vstart := outVecCtrl.vstart 426 mgu.io.in.info.vlmul := outVecCtrl.vlmul 427 mgu.io.in.info.valid := Mux(notModifyVd, false.B, io.in.valid) 428 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 429 mgu.io.in.info.eew := RegEnable(outEew_s0,io.in.fire) 430 mgu.io.in.info.vsew := outVecCtrl.vsew 431 mgu.io.in.info.vdIdx := RegEnable(Mux(outIsResuction_s0, 0.U, outVecCtrl_s0.vuopIdx), io.in.fire) 432 mgu.io.in.info.narrow := outVecCtrl.isNarrow 433 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 434 mgu.io.in.isIndexedVls := false.B 435 mgtu.io.in.vd := Mux(outVecCtrl.isDstMask, mgu.io.out.vd, resultDataUInt) 436 mgtu.io.in.vl := outVl 437 val resultFpMask = Wire(UInt(VLEN.W)) 438 val isFclass = outVecCtrl.fpu.isFpToVecInst && (outCtrl.fuOpType === VfaluType.vfclass) 439 val fpCmpFuOpType = Seq(VfaluType.vfeq, VfaluType.vflt, VfaluType.vfle) 440 val isCmp = outVecCtrl.fpu.isFpToVecInst && (fpCmpFuOpType.map(_ === outCtrl.fuOpType).reduce(_|_)) 441 resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W))) 442 // when dest is mask, the result need to be masked by mgtu 443 io.out.bits.res.data := Mux(notModifyVd, outOldVd, Mux(outVecCtrl.isDstMask, mgtu.io.out.vd, mgu.io.out.vd) & resultFpMask) 444 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 445 446} 447 448class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{ 449 val io = IO(new VFMguIO(vlen)) 450 451 val vd = io.in.vd 452 val oldvd = io.in.oldVd 453 val mask = io.in.mask 454 val vsew = io.in.info.eew 455 val num16bits = vlen / 16 456 457} 458 459class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle { 460 val in = new Bundle { 461 val vd = Input(UInt(vlen.W)) 462 val oldVd = Input(UInt(vlen.W)) 463 val mask = Input(UInt(vlen.W)) 464 val info = Input(new VecInfo) 465 } 466 val out = new Bundle { 467 val vd = Output(UInt(vlen.W)) 468 } 469}