1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.{VLmul, VSew, ma} 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Mgtu, VecInfo, VecPipedFuncUnit} 11import xiangshan.ExceptionNO 12import yunsuan.{VfaluType, VfpuType} 13import yunsuan.vector.VectorFloatAdder 14import xiangshan.backend.fu.vector.Bundles.VConfig 15 16class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 17 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 18 19 // params alias 20 private val dataWidth = cfg.destDataBits 21 private val dataWidthOfDataModule = 64 22 private val numVecModule = dataWidth / dataWidthOfDataModule 23 24 // io alias 25 private val opcode = fuOpType(4,0) 26 private val resWiden = fuOpType(5) 27 private val opbWiden = fuOpType(6) 28 29 // modules 30 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 31 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 34 private val mgu = Module(new Mgu(dataWidth)) 35 private val mgtu = Module(new Mgtu(dataWidth)) 36 37 /** 38 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 39 */ 40 vs2Split.io.inVecData := vs2 41 vs1Split.io.inVecData := vs1 42 oldVdSplit.io.inVecData := oldVd 43 44 /** 45 * [[vfalus]]'s in connection 46 */ 47 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 48 // Vec( 49 // Cat(vs2(95,64), vs2(31,0)), 50 // Cat(vs2(127,96), vs2(63,32)), 51 // ) 52 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 53 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 54 private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W))) 55 private val fflagsData = Wire(Vec(numVecModule,UInt(20.W))) 56 private val srcMaskRShiftForReduction = Wire(UInt((8 * numVecModule).W)) 57 // for reduction 58 val isFirstGroupUop = vuopIdx === 0.U || 59 (vuopIdx === 1.U && (vlmul === VLmul.m4 || vlmul === VLmul.m8)) || 60 ((vuopIdx === 2.U || vuopIdx === 3.U) && vlmul === VLmul.m8) 61 val maskRshiftWidthForReduction = Wire(UInt(6.W)) 62 maskRshiftWidthForReduction := Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 63 vuopIdx, 64 Mux1H(Seq( 65 (vsew === VSew.e16) -> (vuopIdx(1, 0) << 4), 66 (vsew === VSew.e32) -> (vuopIdx(1, 0) << 3), 67 (vsew === VSew.e64) -> (vuopIdx(1, 0) << 2), 68 )) 69 ) 70 val vlMaskForReduction = (~(Fill(VLEN, 1.U) << vl)).asUInt 71 srcMaskRShiftForReduction := ((srcMask & vlMaskForReduction) >> maskRshiftWidthForReduction)(8 * numVecModule - 1, 0) 72 val existMask = (srcMask & vlMaskForReduction).orR 73 val existMaskReg = RegEnable(existMask, io.in.fire) 74 75 76 def genMaskForReduction(inmask: UInt, sew: UInt, i: Int): UInt = { 77 val f64MaskNum = dataWidth / 64 * 2 78 val f32MaskNum = dataWidth / 32 * 2 79 val f16MaskNum = dataWidth / 16 * 2 80 val f64Mask = inmask(f64MaskNum - 1, 0) 81 val f32Mask = inmask(f32MaskNum - 1, 0) 82 val f16Mask = inmask(f16MaskNum - 1, 0) 83 // vs2 reordered, so mask use high bits 84 val f64FirstFoldMaskUnorder = Mux1H( 85 Seq( 86 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(0), 0.U(3.W), f64Mask(1)), 87 ) 88 ) 89 val f64FirstFoldMaskOrder = Mux1H( 90 Seq( 91 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(1), 0.U(3.W), f64Mask(0)) 92 ) 93 ) 94 val f32FirstFoldMaskUnorder = Mux1H( 95 Seq( 96 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(1), f32Mask(0), 0.U(2.W), f32Mask(3), f32Mask(2)), 97 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(0), 0.U(3.W), f32Mask(1)), 98 ) 99 ) 100 val f32FirstFoldMaskOrder = Mux1H( 101 Seq( 102 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(3), f32Mask(2), 0.U(2.W), f32Mask(1), f32Mask(0)), 103 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(1), 0.U(3.W), f32Mask(0)), 104 ) 105 ) 106 val f16FirstFoldMaskUnorder = Mux1H( 107 Seq( 108 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 109 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(1), f16Mask(0), 0.U(2.W), f16Mask(3), f16Mask(2)), 110 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(0), 0.U(3.W), f16Mask(1)), 111 ) 112 ) 113 val f16FirstFoldMaskOrder = Mux1H( 114 Seq( 115 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 116 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(3), f16Mask(2), 0.U(2.W), f16Mask(1), f16Mask(0)), 117 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(1), 0.U(3.W), f16Mask(0)), 118 ) 119 ) 120 val f64FoldMask = Mux1H( 121 Seq( 122 vecCtrl.fpu.isFoldTo1_2 -> "b00010001".U, 123 ) 124 ) 125 val f32FoldMask = Mux1H( 126 Seq( 127 vecCtrl.fpu.isFoldTo1_2 -> "b00110011".U, 128 vecCtrl.fpu.isFoldTo1_4 -> "b00010001".U, 129 ) 130 ) 131 val f16FoldMask = Mux1H( 132 Seq( 133 vecCtrl.fpu.isFoldTo1_2 -> "b11111111".U, 134 vecCtrl.fpu.isFoldTo1_4 -> "b00110011".U, 135 vecCtrl.fpu.isFoldTo1_8 -> "b00010001".U, 136 ) 137 ) 138 // low 4 bits for vs2(fp_a), high 4 bits for vs1(fp_b), 139 val isFold = vecCtrl.fpu.isFoldTo1_2 || vecCtrl.fpu.isFoldTo1_4 || vecCtrl.fpu.isFoldTo1_8 140 val f64FirstNotFoldMask = Cat(0.U(3.W), f64Mask(i + 2), 0.U(3.W), f64Mask(i)) 141 val f32FirstNotFoldMask = Cat(0.U(2.W), f32Mask(i * 2 + 5, i * 2 + 4), 0.U(2.W), Cat(f32Mask(i * 2 + 1, i * 2))) 142 val f16FirstNotFoldMask = Cat(f16Mask(i * 4 + 11, i * 4 + 8), f16Mask(i * 4 + 3, i * 4)) 143 val f64MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 144 Mux(isFold, f64FirstFoldMaskOrder, f64FirstNotFoldMask), 145 Mux(isFirstGroupUop, 146 Mux(isFold, f64FirstFoldMaskUnorder, f64FirstNotFoldMask), 147 Mux(isFold, f64FoldMask, Fill(8, 1.U)))) 148 val f32MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 149 Mux(isFold, f32FirstFoldMaskOrder, f32FirstNotFoldMask), 150 Mux(isFirstGroupUop, 151 Mux(isFold, f32FirstFoldMaskUnorder, f32FirstNotFoldMask), 152 Mux(isFold, f32FoldMask, Fill(8, 1.U)))) 153 val f16MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 154 Mux(isFold, f16FirstFoldMaskOrder, f16FirstNotFoldMask), 155 Mux(isFirstGroupUop, 156 Mux(isFold, f16FirstFoldMaskUnorder, f16FirstNotFoldMask), 157 Mux(isFold, f16FoldMask, Fill(8, 1.U)))) 158 val outMask = Mux1H( 159 Seq( 160 (sew === 3.U) -> f64MaskI, 161 (sew === 2.U) -> f32MaskI, 162 (sew === 1.U) -> f16MaskI, 163 ) 164 ) 165 Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, outMask(0),outMask) 166 } 167 def genMaskForMerge(inmask:UInt, sew:UInt, i:Int): UInt = { 168 val f64MaskNum = dataWidth / 64 169 val f32MaskNum = dataWidth / 32 170 val f16MaskNum = dataWidth / 16 171 val f64Mask = inmask(f64MaskNum-1,0) 172 val f32Mask = inmask(f32MaskNum-1,0) 173 val f16Mask = inmask(f16MaskNum-1,0) 174 val f64MaskI = Cat(0.U(3.W),f64Mask(i)) 175 val f32MaskI = Cat(0.U(2.W),f32Mask(2*i+1,2*i)) 176 val f16MaskI = f16Mask(4*i+3,4*i) 177 val outMask = Mux1H( 178 Seq( 179 (sew === 3.U) -> f64MaskI, 180 (sew === 2.U) -> f32MaskI, 181 (sew === 1.U) -> f16MaskI, 182 ) 183 ) 184 outMask 185 } 186 val isScalarMove = (fuOpType === VfaluType.vfmv_f_s) || (fuOpType === VfaluType.vfmv_s_f) 187 val srcMaskRShift = Wire(UInt((4 * numVecModule).W)) 188 val maskRshiftWidth = Wire(UInt(6.W)) 189 maskRshiftWidth := Mux1H( 190 Seq( 191 (vsew === VSew.e16) -> (vuopIdx(2,0) << 3), 192 (vsew === VSew.e32) -> (vuopIdx(2,0) << 2), 193 (vsew === VSew.e64) -> (vuopIdx(2,0) << 1), 194 ) 195 ) 196 srcMaskRShift := (srcMask >> maskRshiftWidth)(4 * numVecModule - 1, 0) 197 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 198 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 199 val inIsFold = Wire(UInt(3.W)) 200 inIsFold := Cat(vecCtrl.fpu.isFoldTo1_8, vecCtrl.fpu.isFoldTo1_4, vecCtrl.fpu.isFoldTo1_2) 201 vfalus.zipWithIndex.foreach { 202 case (mod, i) => 203 mod.io.fire := io.in.valid 204 mod.io.fp_a := vs2Split.io.outVec64b(i) 205 mod.io.fp_b := vs1Split.io.outVec64b(i) 206 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 207 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 208 mod.io.frs1 := 0.U // already vf -> vv 209 mod.io.is_frs1 := false.B // already vf -> vv 210 mod.io.mask := Mux(isScalarMove, !vuopIdx.orR, genMaskForMerge(inmask = srcMaskRShift, sew = vsew, i = i)) 211 mod.io.maskForReduction := genMaskForReduction(inmask = srcMaskRShiftForReduction, sew = vsew, i = i) 212 mod.io.uop_idx := vuopIdx(0) 213 mod.io.is_vec := true.B // Todo 214 mod.io.round_mode := rm 215 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 216 mod.io.opb_widening := opbWiden 217 mod.io.res_widening := resWiden 218 mod.io.op_code := opcode 219 mod.io.is_vfwredosum := fuOpType === VfaluType.vfwredosum 220 mod.io.is_fold := inIsFold 221 mod.io.vs2_fold := vs2 // for better timing 222 resultData(i) := mod.io.fp_result 223 fflagsData(i) := mod.io.fflags 224 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 225 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 226 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 227 ) 228 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 229 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 230 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 231 ) 232 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 233 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 234 } 235 val numOfUopVFRED = Wire(UInt(4.W)) 236 val numofUopVFREDReg = RegEnable(numOfUopVFRED, io.in.fire) 237 val vs1Reg = RegEnable(vs1, io.in.fire) 238 val isVfRed = outCtrl.fuOpType === VfaluType.vfredusum || 239 outCtrl.fuOpType === VfaluType.vfredmax || 240 outCtrl.fuOpType === VfaluType.vfredmin 241 val isLastUop = isVfRed && (outCtrl.vpu.get.vuopIdx === numofUopVFREDReg - 1.U) 242 val resultDataUInt = Mux(isLastUop && !existMaskReg, vs1Reg, resultData.asUInt) 243 val cmpResultWidth = dataWidth / 16 244 val cmpResult = Wire(Vec(cmpResultWidth, Bool())) 245 for (i <- 0 until cmpResultWidth) { 246 if(i == 0) { 247 cmpResult(i) := resultDataUInt(0) 248 } 249 else if(i < dataWidth / 64) { 250 cmpResult(i) := Mux1H( 251 Seq( 252 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i*16), 253 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i*32), 254 (outVecCtrl.vsew === 3.U) -> resultDataUInt(i*64) 255 ) 256 ) 257 } 258 else if(i < dataWidth / 32) { 259 cmpResult(i) := Mux1H( 260 Seq( 261 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i * 16), 262 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i * 32), 263 (outVecCtrl.vsew === 3.U) -> false.B 264 ) 265 ) 266 } 267 else if(i < dataWidth / 16) { 268 cmpResult(i) := Mux(outVecCtrl.vsew === 1.U, resultDataUInt(i*16), false.B) 269 } 270 } 271 val outCtrl_s0 = ctrlVec.head 272 val outVecCtrl_s0 = ctrlVec.head.vpu.get 273 val outEew_s0 = Mux(resWiden, outVecCtrl_s0.vsew + 1.U, outVecCtrl_s0.vsew) 274 val outEew = Mux(RegEnable(resWiden, io.in.fire), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 275 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 276 val vlMax_s0 = ((VLEN/8).U >> outEew_s0).asUInt 277 val vlMax = ((VLEN/8).U >> outEew).asUInt 278 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1,0)).asUInt + 1.U, outVecCtrl.vlmul(1,0)) 279 // vfmv_f_s need vl=1, reduction last uop need vl=1, other uop need vl=vlmax 280 numOfUopVFRED := { 281 // addTime include add frs1 282 val addTime = MuxLookup(outVecCtrl_s0.vlmul, 1.U(4.W))(Array( 283 VLmul.m2 -> 2.U, 284 VLmul.m4 -> 4.U, 285 VLmul.m8 -> 8.U, 286 )) 287 val foldLastVlmul = MuxLookup(outVecCtrl_s0.vsew, "b000".U)(Array( 288 VSew.e16 -> VLmul.mf8, 289 VSew.e32 -> VLmul.mf4, 290 VSew.e64 -> VLmul.mf2, 291 )) 292 // lmul < 1, foldTime = vlmul - foldFastVlmul 293 // lmul >= 1, foldTime = 0.U - foldFastVlmul 294 val foldTime = Mux(outVecCtrl_s0.vlmul(2), outVecCtrl_s0.vlmul, 0.U) - foldLastVlmul 295 addTime + foldTime 296 } 297 val reductionVl = Mux((outVecCtrl_s0.vuopIdx === numOfUopVFRED - 1.U) || (outCtrl_s0.fuOpType === VfaluType.vfredosum || outCtrl_s0.fuOpType === VfaluType.vfwredosum), 1.U, vlMax_s0) 298 val outIsResuction = outCtrl.fuOpType === VfaluType.vfredusum || 299 outCtrl.fuOpType === VfaluType.vfredmax || 300 outCtrl.fuOpType === VfaluType.vfredmin || 301 outCtrl.fuOpType === VfaluType.vfredosum || 302 outCtrl.fuOpType === VfaluType.vfwredosum 303 val outIsResuction_s0 = outCtrl_s0.fuOpType === VfaluType.vfredusum || 304 outCtrl_s0.fuOpType === VfaluType.vfredmax || 305 outCtrl_s0.fuOpType === VfaluType.vfredmin || 306 outCtrl_s0.fuOpType === VfaluType.vfredosum || 307 outCtrl_s0.fuOpType === VfaluType.vfwredosum 308 val outVConfig_s0 = if(!cfg.vconfigWakeUp) outVecCtrl_s0.vconfig else dataVec.head.getSrcVConfig.asTypeOf(new VConfig) 309 val outVl_s0 = outVConfig_s0.vl 310 val outVlFix_s0 = Mux( 311 outVecCtrl_s0.fpu.isFpToVecInst || (outCtrl_s0.fuOpType === VfaluType.vfmv_f_s), 312 1.U, 313 Mux( 314 outCtrl_s0.fuOpType === VfaluType.vfmv_s_f, 315 outVl_s0.orR, 316 Mux(outIsResuction_s0, reductionVl, outVl_s0) 317 ) 318 ) 319 val outVlFix = RegEnable(outVlFix_s0,io.in.fire) 320 321 val vlMaxAllUop = Wire(outVl.cloneType) 322 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 323 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 324 val vlSetThisUop = Mux(outVlFix > outVuopidx*vlMaxThisUop, outVlFix - outVuopidx*vlMaxThisUop, 0.U) 325 val vlThisUop = Wire(UInt(3.W)) 326 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 327 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 328 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 329 330 private val needNoMask = outCtrl.fuOpType === VfaluType.vfmerge || 331 outCtrl.fuOpType === VfaluType.vfmv_s_f || 332 outIsResuction || 333 outVecCtrl.fpu.isFpToVecInst 334 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 335 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 336 val outSrcMaskRShift = Wire(UInt((4*numVecModule).W)) 337 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2,0) * vlMax))(4*numVecModule-1,0) 338 val f16FFlagsEn = outSrcMaskRShift 339 val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W))) 340 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 341 val f16VlMaskEn = vlMaskRShift 342 val f32VlMaskEn = Wire(Vec(numVecModule, UInt(4.W))) 343 val f64VlMaskEn = Wire(Vec(numVecModule, UInt(4.W))) 344 for (i <- 0 until numVecModule){ 345 f32FFlagsEn(i) := Cat(Fill(2, 0.U), outSrcMaskRShift(2*i+1,2*i)) 346 f64FFlagsEn(i) := Cat(Fill(3, 0.U), outSrcMaskRShift(i)) 347 f32VlMaskEn(i) := Cat(Fill(2, 0.U), vlMaskRShift(2 * i + 1, 2 * i)) 348 f64VlMaskEn(i) := Cat(Fill(3, 0.U), vlMaskRShift(i)) 349 } 350 val fflagsEn= Mux1H( 351 Seq( 352 (outEew === 1.U) -> f16FFlagsEn.asUInt, 353 (outEew === 2.U) -> f32FFlagsEn.asUInt, 354 (outEew === 3.U) -> f64FFlagsEn.asUInt 355 ) 356 ) 357 val vlMaskEn = Mux1H( 358 Seq( 359 (outEew === 1.U) -> f16VlMaskEn.asUInt, 360 (outEew === 2.U) -> f32VlMaskEn.asUInt, 361 (outEew === 3.U) -> f64VlMaskEn.asUInt 362 ) 363 ) 364 allFFlagsEn := Mux(outIsResuction, Fill(4*numVecModule, 1.U), (fflagsEn & vlMaskEn)).asTypeOf(allFFlagsEn) 365 366 val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W))) 367 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 368 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 369 }.reduce(_ | _) 370 io.out.bits.res.fflags.get := outFFlags 371 372 373 val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) 374 val cmpResultOldVdRshiftWidth = Wire(UInt(6.W)) 375 cmpResultOldVdRshiftWidth := Mux1H( 376 Seq( 377 (outVecCtrl.vsew === VSew.e16) -> (outVecCtrl.vuopIdx(2, 0) << 3), 378 (outVecCtrl.vsew === VSew.e32) -> (outVecCtrl.vuopIdx(2, 0) << 2), 379 (outVecCtrl.vsew === VSew.e64) -> (outVecCtrl.vuopIdx(2, 0) << 1), 380 ) 381 ) 382 cmpResultOldVd := (outOldVd >> cmpResultOldVdRshiftWidth)(4*numVecModule-1,0) 383 val cmpResultForMgu = Wire(Vec(cmpResultWidth, Bool())) 384 private val maxVdIdx = 8 385 private val elementsInOneUop = Mux1H( 386 Seq( 387 (outEew === 1.U) -> (cmpResultWidth).U(4.W), 388 (outEew === 2.U) -> (cmpResultWidth / 2).U(4.W), 389 (outEew === 3.U) -> (cmpResultWidth / 4).U(4.W), 390 ) 391 ) 392 private val vdIdx = outVecCtrl.vuopIdx(2, 0) 393 private val elementsComputed = Mux1H(Seq.tabulate(maxVdIdx)(i => (vdIdx === i.U) -> (elementsInOneUop * i.U))) 394 for (i <- 0 until cmpResultWidth) { 395 val cmpResultWithVmask = Mux(outSrcMaskRShift(i), cmpResult(i), Mux(outVecCtrl.vma, true.B, cmpResultOldVd(i))) 396 cmpResultForMgu(i) := Mux(elementsComputed +& i.U >= outVl, true.B, cmpResultWithVmask) 397 } 398 val outIsFold = outVecCtrl.fpu.isFoldTo1_2 || outVecCtrl.fpu.isFoldTo1_4 || outVecCtrl.fpu.isFoldTo1_8 399 val outOldVdForREDO = Mux1H(Seq( 400 (outVecCtrl.vsew === VSew.e16) -> (outOldVd >> 16), 401 (outVecCtrl.vsew === VSew.e32) -> (outOldVd >> 32), 402 (outVecCtrl.vsew === VSew.e64) -> (outOldVd >> 64), 403 )) 404 val outOldVdForWREDO = Mux( 405 !outIsFold, 406 Mux(outVecCtrl.vsew === VSew.e16, Cat(outOldVd(VLEN-1-16,16), 0.U(32.W)), Cat(outOldVd(VLEN-1-32,32), 0.U(64.W))), 407 Mux(outVecCtrl.vsew === VSew.e16, 408 // Divide vuopIdx by 8 and the remainder is 1 409 Mux(outVecCtrl.vuopIdx(2,0) === 1.U, outOldVd, outOldVd >> 16), 410 // Divide vuopIdx by 4 and the remainder is 1 411 Mux(outVecCtrl.vuopIdx(1,0) === 1.U, outOldVd, outOldVd >> 32) 412 ), 413 ) 414 val outOldVdForRED = Mux(outCtrl.fuOpType === VfaluType.vfredosum, outOldVdForREDO, outOldVdForWREDO) 415 val numOfUopVFREDOSUM = { 416 val uvlMax = MuxLookup(outVecCtrl.vsew, 0.U)(Array( 417 VSew.e16 -> 8.U, 418 VSew.e32 -> 4.U, 419 VSew.e64 -> 2.U, 420 )) 421 val vlMax = Mux(outVecCtrl.vlmul(2), uvlMax >> (-outVecCtrl.vlmul)(1, 0), uvlMax << outVecCtrl.vlmul(1, 0)).asUInt 422 vlMax 423 } 424 val isOutOldVdForREDO = (outCtrl.fuOpType === VfaluType.vfredosum && outIsFold) || outCtrl.fuOpType === VfaluType.vfwredosum 425 val taIsFalseForVFREDO = ((outCtrl.fuOpType === VfaluType.vfredosum) || (outCtrl.fuOpType === VfaluType.vfwredosum)) && (outVecCtrl.vuopIdx =/= numOfUopVFREDOSUM - 1.U) 426 // outVecCtrl.fpu.isFpToVecInst means the instruction is float instruction, not vector float instruction 427 val notUseVl = outVecCtrl.fpu.isFpToVecInst || (outCtrl.fuOpType === VfaluType.vfmv_f_s) 428 val notModifyVd = !notUseVl && (outVl === 0.U) 429 mgu.io.in.vd := Mux(outVecCtrl.isDstMask, Cat(0.U((dataWidth / 16 * 15).W), cmpResultForMgu.asUInt), resultDataUInt) 430 mgu.io.in.oldVd := Mux(isOutOldVdForREDO, outOldVdForRED, outOldVd) 431 mgu.io.in.mask := maskToMgu 432 mgu.io.in.info.ta := Mux(outCtrl.fuOpType === VfaluType.vfmv_f_s, true.B , Mux(taIsFalseForVFREDO, false.B, outVecCtrl.vta)) 433 mgu.io.in.info.ma := Mux(outCtrl.fuOpType === VfaluType.vfmv_s_f, true.B , outVecCtrl.vma) 434 mgu.io.in.info.vl := outVlFix 435 mgu.io.in.info.vstart := outVecCtrl.vstart 436 mgu.io.in.info.vlmul := outVecCtrl.vlmul 437 mgu.io.in.info.valid := Mux(notModifyVd, false.B, io.in.valid) 438 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 439 mgu.io.in.info.eew := RegEnable(outEew_s0,io.in.fire) 440 mgu.io.in.info.vsew := outVecCtrl.vsew 441 mgu.io.in.info.vdIdx := RegEnable(Mux(outIsResuction_s0, 0.U, outVecCtrl_s0.vuopIdx), io.in.fire) 442 mgu.io.in.info.narrow := outVecCtrl.isNarrow 443 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 444 mgu.io.in.isIndexedVls := false.B 445 mgtu.io.in.vd := Mux(outVecCtrl.isDstMask, mgu.io.out.vd, resultDataUInt) 446 mgtu.io.in.vl := outVl 447 val resultFpMask = Wire(UInt(VLEN.W)) 448 val isFclass = outVecCtrl.fpu.isFpToVecInst && (outCtrl.fuOpType === VfaluType.vfclass) 449 val fpCmpFuOpType = Seq(VfaluType.vfeq, VfaluType.vflt, VfaluType.vfle) 450 val isCmp = outVecCtrl.fpu.isFpToVecInst && (fpCmpFuOpType.map(_ === outCtrl.fuOpType).reduce(_|_)) 451 resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W))) 452 // when dest is mask, the result need to be masked by mgtu 453 io.out.bits.res.data := Mux(notModifyVd, outOldVd, Mux(outVecCtrl.isDstMask, mgtu.io.out.vd, mgu.io.out.vd) & resultFpMask) 454 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 455 456} 457 458class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{ 459 val io = IO(new VFMguIO(vlen)) 460 461 val vd = io.in.vd 462 val oldvd = io.in.oldVd 463 val mask = io.in.mask 464 val vsew = io.in.info.eew 465 val num16bits = vlen / 16 466 467} 468 469class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle { 470 val in = new Bundle { 471 val vd = Input(UInt(vlen.W)) 472 val oldVd = Input(UInt(vlen.W)) 473 val mask = Input(UInt(vlen.W)) 474 val info = Input(new VecInfo) 475 } 476 val out = new Bundle { 477 val vd = Output(UInt(vlen.W)) 478 } 479}