1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.fpu.FpPipedFuncUnit 10import yunsuan.{VfmaType, VfpuType} 11import yunsuan.vector.VectorFloatFMA 12import yunsuan.fpulite.FloatFMA 13 14class FMA(cfg: FuConfig)(implicit p: Parameters) extends FpPipedFuncUnit(cfg) { 15 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "fma OpType not supported") 16 17 // io alias 18 private val opcode = fuOpType(3, 0) 19 private val src0 = inData.src(0) 20 private val src1 = inData.src(1) 21 private val src2 = inData.src(2) 22 23 // modules 24 private val fma = Module(new FloatFMA) 25 26 val fp_aIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src1.head(32).andR || 27 fp_fmt === VSew.e16 && !src1.head(48).andR 28 val fp_bIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src0.head(32).andR || 29 fp_fmt === VSew.e16 && !src0.head(48).andR 30 val fp_cIsFpCanonicalNAN = !(opcode === VfmaType.vfmul) && (fp_fmt === VSew.e32 && !src2.head(32).andR || 31 fp_fmt === VSew.e16 && !src2.head(48).andR) 32 33 fma.io.fire := io.in.valid 34 fma.io.fp_a := src1 35 fma.io.fp_b := src0 36 fma.io.fp_c := src2 37 fma.io.round_mode := rm 38 fma.io.fp_format := fp_fmt 39 fma.io.op_code := opcode 40 fma.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN 41 fma.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN 42 fma.io.fp_cIsFpCanonicalNAN := fp_cIsFpCanonicalNAN 43 44 private val resultData = fma.io.fp_result 45 private val fflagsData = fma.io.fflags 46 47 io.out.bits.res.fflags.get := fflagsData 48 io.out.bits.res.data := resultData 49} 50