1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.fpu.FpNonPipedFuncUnit 10import xiangshan.backend.rob.RobPtr 11import yunsuan.VfpuType 12import yunsuan.vector.VectorFloatDivider 13import yunsuan.fpulite.FloatDivider 14 15class FDivSqrt(cfg: FuConfig)(implicit p: Parameters) extends FpNonPipedFuncUnit(cfg) { 16 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "fdiv OpType not supported") 17 18 // io alias 19 private val opcode = fuOpType(0) 20 private val src0 = inData.src(0) 21 private val src1 = inData.src(1) 22 23 // modules 24 private val fdiv = Module(new FloatDivider) 25 26 val fp_aIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src1.head(32).andR || 27 fp_fmt === VSew.e16 && !src1.head(48).andR 28 val fp_bIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src0.head(32).andR || 29 fp_fmt === VSew.e16 && !src0.head(48).andR 30 31 val thisRobIdx = Wire(new RobPtr) 32 when(io.in.ready){ 33 thisRobIdx := io.in.bits.ctrl.robIdx 34 }.otherwise{ 35 thisRobIdx := outCtrl.robIdx 36 } 37 38 fdiv.io.start_valid_i := io.in.valid 39 fdiv.io.finish_ready_i := io.out.ready & io.out.valid 40 fdiv.io.flush_i := thisRobIdx.needFlush(io.flush) 41 fdiv.io.fp_format_i := fp_fmt 42 fdiv.io.opa_i := src1 43 fdiv.io.opb_i := src0 44 fdiv.io.is_sqrt_i := opcode 45 fdiv.io.rm_i := rm 46 fdiv.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN 47 fdiv.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN 48 49 private val resultData = Mux1H( 50 Seq( 51 (outCtrl.vpu.get.vsew === VSew.e16) -> Cat(Fill(48, 1.U), fdiv.io.fpdiv_res_o(15, 0)), 52 (outCtrl.vpu.get.vsew === VSew.e32) -> Cat(Fill(32, 1.U), fdiv.io.fpdiv_res_o(31, 0)), 53 (outCtrl.vpu.get.vsew === VSew.e64) -> fdiv.io.fpdiv_res_o 54 ) 55 ) 56 private val fflagsData = fdiv.io.fflags_o 57 58 io.in.ready := fdiv.io.start_ready_o 59 io.out.valid := fdiv.io.finish_valid_o 60 61 io.out.bits.res.fflags.get := fflagsData 62 io.out.bits.res.data := resultData 63} 64