1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.frontend.FtqPtr 19 20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 21 with HasCircularQueuePtrHelper 22{ 23 val csrIn = io.csrio.get 24 val csrOut = io.csrio.get 25 val csrToDecode = io.csrToDecode.get 26 27 val setFsDirty = csrIn.fpu.dirty_fs 28 val setFflags = csrIn.fpu.fflags 29 30 val setVsDirty = csrIn.vpu.dirty_vs 31 val setVstart = csrIn.vpu.set_vstart 32 val setVtype = csrIn.vpu.set_vtype 33 val setVxsat = csrIn.vpu.set_vxsat 34 val vlFromPreg = csrIn.vpu.vl 35 36 val flushPipe = Wire(Bool()) 37 val flush = io.flush.valid 38 39 val (valid, src1, imm, func) = ( 40 io.in.valid, 41 io.in.bits.data.src(0), 42 io.in.bits.data.imm(Imm_Z().len - 1, 0), 43 io.in.bits.ctrl.fuOpType 44 ) 45 46 // split imm/src1/rd from IMM_Z: src1/rd for tval 47 val addr = Imm_Z().getCSRAddr(imm) 48 val rd = Imm_Z().getRD(imm) 49 val rs1 = Imm_Z().getRS1(imm) 50 val imm5 = Imm_Z().getImm5(imm) 51 val csri = ZeroExt(imm5, XLEN) 52 53 import CSRConst._ 54 55 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 56 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 57 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 58 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 59 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 60 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 61 private val isWfi = CSROpType.isWfi(func) 62 private val isCSRAcc = CSROpType.isCsrAccess(func) 63 64 val csrMod = Module(new NewCSR) 65 val trapInstMod = Module(new TrapInstMod) 66 67 private val privState = csrMod.io.status.privState 68 // The real reg value in CSR, with no read mask 69 private val regOut = csrMod.io.out.bits.regOut 70 private val src = Mux(CSROpType.needImm(func), csri, src1) 71 private val wdata = LookupTree(func, Seq( 72 CSROpType.wrt -> src1, 73 CSROpType.set -> (regOut | src1), 74 CSROpType.clr -> (regOut & (~src1).asUInt), 75 CSROpType.wrti -> csri, 76 CSROpType.seti -> (regOut | csri), 77 CSROpType.clri -> (regOut & (~csri).asUInt), 78 )) 79 80 private val csrAccess = valid && CSROpType.isCsrAccess(func) 81 private val csrWen = valid && ( 82 CSROpType.isCSRRW(func) || 83 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 84 ) 85 private val csrRen = valid && ( 86 CSROpType.isCSRRW(func) && rd =/= 0.U || 87 CSROpType.isCSRRSorRC(func) 88 ) 89 90 csrMod.io.in match { 91 case in => 92 in.valid := valid 93 in.bits.wen := csrWen 94 in.bits.ren := csrRen 95 in.bits.op := CSROpType.getCSROp(func) 96 in.bits.addr := addr 97 in.bits.src := src 98 in.bits.wdata := wdata 99 in.bits.mret := isMret 100 in.bits.mnret := isMNret 101 in.bits.sret := isSret 102 in.bits.dret := isDret 103 } 104 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 105 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 106 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 107 108 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 109 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 110 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 111 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 112 // Todo: shrink the width of trap vector. 113 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 114 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 115 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 116 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 117 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 118 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 119 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 120 121 csrMod.io.fromRob.commit.fflags := setFflags 122 csrMod.io.fromRob.commit.fsDirty := setFsDirty 123 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 124 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 125 csrMod.io.fromRob.commit.vsDirty := setVsDirty 126 csrMod.io.fromRob.commit.vstart := setVstart 127 csrMod.io.fromRob.commit.vl := vlFromPreg 128 // Todo: correct vtype 129 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 130 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 131 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 132 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 133 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 134 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 135 136 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 137 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 138 139 csrMod.io.perf := csrIn.perf 140 141 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 142 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 143 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 144 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 145 csrMod.platformIRP.STIP := false.B 146 csrMod.platformIRP.VSEIP := false.B // Todo 147 csrMod.platformIRP.VSTIP := false.B // Todo 148 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 149 csrMod.nonMaskableIRP.NMI := csrIn.externalInterrupt.nmi.nmi 150 151 csrMod.io.fromTop.hartId := io.csrin.get.hartId 152 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 153 private val csrModOutValid = csrMod.io.out.valid 154 private val csrModOut = csrMod.io.out.bits 155 156 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 157 trapInstMod.io.fromRob.flush.valid := io.flush.valid 158 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 159 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 160 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 161 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 162 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 163 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 164 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 165 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 166 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 167 case t => 168 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 169 }) 170 171 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 172 imsic.i.hartId := io.csrin.get.hartId 173 imsic.i.msiInfo := io.csrin.get.msiInfo 174 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 175 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 176 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 177 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 178 imsic.i.csr.vgein := csrMod.toAIA.vgein 179 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 180 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 181 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 182 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 183 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 184 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 185 186 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 187 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 188 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 189 csrMod.fromAIA.meip := imsic.o.meip 190 csrMod.fromAIA.seip := imsic.o.seip 191 csrMod.fromAIA.vseip := imsic.o.vseip 192 csrMod.fromAIA.mtopei := imsic.o.mtopei 193 csrMod.fromAIA.stopei := imsic.o.stopei 194 csrMod.fromAIA.vstopei := imsic.o.vstopei 195 196 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 197 198 exceptionVec(EX_BP ) := isEbreak 199 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 200 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 201 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 202 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 203 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 204 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 205 206 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 207 208 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 209 val isXRetFlag = RegInit(false.B) 210 isXRetFlag := Mux1H(Seq( 211 DelayN(flush, 5) -> false.B, 212 isXRet -> true.B, 213 )) 214 215 flushPipe := csrMod.io.out.bits.flushPipe 216 217 // tlb 218 val tlb = Wire(new TlbCsrBundle) 219 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 220 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 221 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 222 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 223 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 224 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 225 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 226 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 227 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 228 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 229 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 230 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 231 232 // expose several csr bits for tlb 233 tlb.priv.mxr := csrMod.io.tlb.mxr 234 tlb.priv.sum := csrMod.io.tlb.sum 235 tlb.priv.vmxr := csrMod.io.tlb.vmxr 236 tlb.priv.vsum := csrMod.io.tlb.vsum 237 tlb.priv.spvp := csrMod.io.tlb.spvp 238 tlb.priv.virt := csrMod.io.tlb.dvirt 239 tlb.priv.imode := csrMod.io.tlb.imode 240 tlb.priv.dmode := csrMod.io.tlb.dmode 241 242 io.in.ready := true.B // Todo: Async read imsic may block CSR 243 io.out.valid := csrModOutValid 244 io.out.bits.ctrl.exceptionVec.get := exceptionVec 245 io.out.bits.ctrl.flushPipe.get := flushPipe 246 io.out.bits.res.data := csrMod.io.out.bits.rData 247 248 io.out.bits.res.redirect.get.valid := isXRet 249 val redirect = io.out.bits.res.redirect.get.bits 250 redirect := 0.U.asTypeOf(redirect) 251 redirect.level := RedirectLevel.flushAfter 252 redirect.robIdx := io.in.bits.ctrl.robIdx 253 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 254 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 255 redirect.cfiUpdate.predTaken := true.B 256 redirect.cfiUpdate.taken := true.B 257 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc 258 // Only mispred will send redirect to frontend 259 redirect.cfiUpdate.isMisPred := true.B 260 261 connect0LatencyCtrlSingal 262 263 // Todo: summerize all difftest skip condition 264 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 265 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 266 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 267 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 268 269 csrOut.isXRet := isXRetFlag 270 271 csrOut.trapTarget := csrMod.io.out.bits.targetPc 272 csrOut.interrupt := csrMod.io.status.interrupt 273 csrOut.wfi_event := csrMod.io.status.wfiEvent 274 275 csrOut.tlb := tlb 276 277 csrOut.debugMode := csrMod.io.status.debugMode 278 279 csrOut.customCtrl match { 280 case custom => 281 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 282 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 283 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 284 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 285 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 286 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 287 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 288 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 289 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 290 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 291 // ICache 292 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 293 // Load violation predictor 294 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 295 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 296 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 297 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 298 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 299 // Branch predictor 300 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 301 // Memory Block 302 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 303 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 304 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 305 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 306 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 307 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 308 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 309 // Rename 310 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 311 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 312 // distribute csr write signal 313 // write to frontend and memory 314 custom.distribute_csr.w.valid := csrWen 315 custom.distribute_csr.w.bits.addr := addr 316 custom.distribute_csr.w.bits.data := wdata 317 // rename single step 318 custom.singlestep := csrMod.io.status.singleStepFlag 319 // trigger 320 custom.frontend_trigger := csrMod.io.status.frontendTrigger 321 custom.mem_trigger := csrMod.io.status.memTrigger 322 // virtual mode 323 custom.virtMode := csrMod.io.status.privState.V.asBool 324 } 325 326 csrToDecode := csrMod.io.toDecode 327} 328 329class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 330 val hartId = Input(UInt(8.W)) 331 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 332 val clintTime = Input(ValidIO(UInt(64.W))) 333 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 334} 335 336class CSRToDecode(implicit p: Parameters) extends XSBundle { 337 val illegalInst = new Bundle { 338 /** 339 * illegal sfence.vma, sinval.vma 340 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 341 */ 342 val sfenceVMA = Bool() 343 344 /** 345 * illegal sfence.w.inval sfence.inval.ir 346 * raise EX_II when isModeHU 347 */ 348 val sfencePart = Bool() 349 350 /** 351 * illegal hfence.gvma, hinval.gvma 352 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 353 * the condition is the same as sfenceVMA 354 */ 355 val hfenceGVMA = Bool() 356 357 /** 358 * illegal hfence.vvma, hinval.vvma 359 * raise EX_II when isModeHU 360 */ 361 val hfenceVVMA = Bool() 362 363 /** 364 * illegal hlv, hlvx, and hsv 365 * raise EX_II when isModeHU && hstatus.HU=0 366 */ 367 val hlsv = Bool() 368 369 /** 370 * decode all fp inst or all vecfp inst 371 * raise EX_II when FS=Off 372 */ 373 val fsIsOff = Bool() 374 375 /** 376 * decode all vec inst 377 * raise EX_II when VS=Off 378 */ 379 val vsIsOff = Bool() 380 381 /** 382 * illegal wfi 383 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 384 */ 385 val wfi = Bool() 386 387 /** 388 * frm reserved 389 * raise EX_II when frm.data > 4 390 */ 391 val frm = Bool() 392 } 393 val virtualInst = new Bundle { 394 /** 395 * illegal sfence.vma, svinval.vma 396 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 397 */ 398 val sfenceVMA = Bool() 399 400 /** 401 * illegal sfence.w.inval sfence.inval.ir 402 * raise EX_VI when isModeVU 403 */ 404 val sfencePart = Bool() 405 406 /** 407 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 408 * raise EX_VI when isModeVS || isModeVU 409 */ 410 val hfence = Bool() 411 412 /** 413 * illegal hlv, hlvx, and hsv 414 * raise EX_VI when isModeVS || isModeVU 415 */ 416 val hlsv = Bool() 417 418 /** 419 * illegal wfi 420 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 421 */ 422 val wfi = Bool() 423 } 424}