1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 14import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 15 16class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 17{ 18 val csrIn = io.csrio.get 19 val csrOut = io.csrio.get 20 val csrToDecode = io.csrToDecode.get 21 22 val setFsDirty = csrIn.fpu.dirty_fs 23 val setFflags = csrIn.fpu.fflags 24 25 val setVsDirty = csrIn.vpu.dirty_vs 26 val setVstart = csrIn.vpu.set_vstart 27 val setVtype = csrIn.vpu.set_vtype 28 val setVxsat = csrIn.vpu.set_vxsat 29 val vlFromPreg = csrIn.vpu.vl 30 31 val flushPipe = Wire(Bool()) 32 val flush = io.flush.valid 33 34 val (valid, src1, src2, func) = ( 35 io.in.valid, 36 io.in.bits.data.src(0), 37 io.in.bits.data.imm, 38 io.in.bits.ctrl.fuOpType 39 ) 40 41 // split imm from IMM_Z 42 val addr = src2(11, 0) 43 val csri = ZeroExt(src2(16, 12), XLEN) 44 45 import CSRConst._ 46 47 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 48 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 49 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 50 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 51 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 52 private val isWfi = CSROpType.isWfi(func) 53 private val isCSRAcc = CSROpType.isCsrAccess(func) 54 55 val csrMod = Module(new NewCSR) 56 57 private val privState = csrMod.io.status.privState 58 // The real reg value in CSR, with no read mask 59 private val regOut = csrMod.io.out.bits.regOut 60 private val src = Mux(CSROpType.needImm(func), csri, src1) 61 private val wdata = LookupTree(func, Seq( 62 CSROpType.wrt -> src1, 63 CSROpType.set -> (regOut | src1), 64 CSROpType.clr -> (regOut & (~src1).asUInt), 65 CSROpType.wrti -> csri, 66 CSROpType.seti -> (regOut | csri), 67 CSROpType.clri -> (regOut & (~csri).asUInt), 68 )) 69 70 private val csrAccess = valid && CSROpType.isCsrAccess(func) 71 private val csrWen = valid && CSROpType.notReadOnly(func) 72 73 csrMod.io.in match { 74 case in => 75 in.valid := valid 76 in.bits.wen := csrWen 77 in.bits.ren := csrAccess 78 in.bits.op := CSROpType.getCSROp(func) 79 in.bits.addr := addr 80 in.bits.src := src 81 in.bits.wdata := wdata 82 in.bits.mret := isMret 83 in.bits.sret := isSret 84 in.bits.dret := isDret 85 } 86 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 87 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 88 89 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 90 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 91 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 92 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 93 // Todo: shrink the width of trap vector. 94 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 95 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 96 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 97 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 98 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 99 csrMod.io.fromRob.trap.bits.triggerCf := csrIn.exception.bits.trigger 100 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 101 102 csrMod.io.fromRob.commit.fflags := setFflags 103 csrMod.io.fromRob.commit.fsDirty := setFsDirty 104 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 105 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 106 csrMod.io.fromRob.commit.vsDirty := setVsDirty 107 csrMod.io.fromRob.commit.vstart := setVstart 108 csrMod.io.fromRob.commit.vl := vlFromPreg 109 // Todo: correct vtype 110 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 111 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 112 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 113 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 114 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 115 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 116 117 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 118 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 119 120 csrMod.io.perf := csrIn.perf 121 122 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 123 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 124 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 125 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 126 csrMod.platformIRP.STIP := false.B 127 csrMod.platformIRP.VSEIP := false.B // Todo 128 csrMod.platformIRP.VSTIP := false.B // Todo 129 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 130 131 csrMod.io.fromTop.hartId := io.csrin.get.hartId 132 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 133 private val csrModOutValid = csrMod.io.out.valid 134 private val csrModOut = csrMod.io.out.bits 135 136 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 137 imsic.i.hartId := io.csrin.get.hartId 138 imsic.i.msiInfo := io.csrin.get.msiInfo 139 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 140 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 141 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 142 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 143 imsic.i.csr.vgein := csrMod.toAIA.vgein 144 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 145 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 146 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 147 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 148 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 149 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 150 151 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 152 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 153 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 154 csrMod.fromAIA.meip := imsic.o.meip 155 csrMod.fromAIA.seip := imsic.o.seip 156 csrMod.fromAIA.vseip := imsic.o.vseip 157 csrMod.fromAIA.mtopei := imsic.o.mtopei 158 csrMod.fromAIA.stopei := imsic.o.stopei 159 csrMod.fromAIA.vstopei := imsic.o.vstopei 160 161 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 162 import ExceptionNO._ 163 exceptionVec(EX_BP ) := isEbreak 164 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 165 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 166 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 167 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 168 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 169 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 170 171 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 172 173 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 174 val isXRetFlag = RegInit(false.B) 175 isXRetFlag := Mux1H(Seq( 176 DelayN(flush, 5) -> false.B, 177 isXRet -> true.B, 178 )) 179 180 flushPipe := csrMod.io.out.bits.flushPipe 181 182 // tlb 183 val tlb = Wire(new TlbCsrBundle) 184 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 185 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 186 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 187 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 188 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 189 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 190 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 191 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 192 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 193 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 194 tlb.hgatp.asid := csrMod.io.tlb.hgatp.VMID.asUInt 195 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 196 197 // expose several csr bits for tlb 198 tlb.priv.mxr := csrMod.io.tlb.mxr 199 tlb.priv.sum := csrMod.io.tlb.sum 200 tlb.priv.vmxr := csrMod.io.tlb.vmxr 201 tlb.priv.vsum := csrMod.io.tlb.vsum 202 tlb.priv.spvp := csrMod.io.tlb.spvp 203 tlb.priv.virt := csrMod.io.tlb.dvirt 204 tlb.priv.imode := csrMod.io.tlb.imode 205 tlb.priv.dmode := csrMod.io.tlb.dmode 206 207 io.in.ready := true.B // Todo: Async read imsic may block CSR 208 io.out.valid := csrModOutValid 209 io.out.bits.ctrl.exceptionVec.get := exceptionVec 210 io.out.bits.ctrl.flushPipe.get := flushPipe 211 io.out.bits.res.data := csrMod.io.out.bits.rData 212 213 io.out.bits.res.redirect.get.valid := isXRet 214 val redirect = io.out.bits.res.redirect.get.bits 215 redirect := 0.U.asTypeOf(redirect) 216 redirect.level := RedirectLevel.flushAfter 217 redirect.robIdx := io.in.bits.ctrl.robIdx 218 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 219 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 220 redirect.cfiUpdate.predTaken := true.B 221 redirect.cfiUpdate.taken := true.B 222 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc 223 // Only mispred will send redirect to frontend 224 redirect.cfiUpdate.isMisPred := true.B 225 226 connect0LatencyCtrlSingal 227 228 // Todo: summerize all difftest skip condition 229 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 230 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 231 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 232 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 233 234 csrOut.isXRet := isXRetFlag 235 236 csrOut.trapTarget := csrMod.io.out.bits.targetPc 237 csrOut.interrupt := csrMod.io.status.interrupt 238 csrOut.wfi_event := csrMod.io.status.wfiEvent 239 240 csrOut.tlb := tlb 241 242 csrOut.debugMode := csrMod.io.status.debugMode 243 244 csrOut.customCtrl match { 245 case custom => 246 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 247 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 248 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 249 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 250 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 251 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 252 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 253 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 254 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 255 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 256 // ICache 257 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 258 // Load violation predictor 259 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 260 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 261 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 262 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 263 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 264 // Branch predictor 265 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 266 // Memory Block 267 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 268 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 269 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 270 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 271 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 272 // Rename 273 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 274 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 275 // distribute csr write signal 276 // write to frontend and memory 277 custom.distribute_csr.w.valid := csrWen 278 custom.distribute_csr.w.bits.addr := addr 279 custom.distribute_csr.w.bits.data := wdata 280 // rename single step 281 custom.singlestep := csrMod.io.status.singleStepFlag 282 // trigger 283 custom.frontend_trigger := csrMod.io.status.frontendTrigger 284 custom.mem_trigger := csrMod.io.status.memTrigger 285 // virtual mode 286 custom.virtMode := csrMod.io.status.privState.V.asBool 287 } 288 289 csrToDecode := csrMod.io.toDecode 290} 291 292class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 293 val hartId = Input(UInt(8.W)) 294 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 295 val clintTime = Input(ValidIO(UInt(64.W))) 296} 297 298class CSRToDecode(implicit p: Parameters) extends XSBundle { 299 val illegalInst = new Bundle { 300 /** 301 * illegal sfence.vma, sinval.vma 302 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 303 */ 304 val sfenceVMA = Bool() 305 306 /** 307 * illegal sfence.w.inval sfence.inval.ir 308 * raise EX_II when isModeHU 309 */ 310 val sfencePart = Bool() 311 312 /** 313 * illegal hfence.gvma, hinval.gvma 314 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 315 * the condition is the same as sfenceVMA 316 */ 317 val hfenceGVMA = Bool() 318 319 /** 320 * illegal hfence.vvma, hinval.vvma 321 * raise EX_II when isModeHU 322 */ 323 val hfenceVVMA = Bool() 324 325 /** 326 * illegal hlv, hlvx, and hsv 327 * raise EX_II when isModeHU && hstatus.HU=0 328 */ 329 val hlsv = Bool() 330 331 /** 332 * decode all fp inst or all vecfp inst 333 * raise EX_II when FS=Off 334 */ 335 val fsIsOff = Bool() 336 337 /** 338 * decode all vec inst 339 * raise EX_II when VS=Off 340 */ 341 val vsIsOff = Bool() 342 343 /** 344 * illegal wfi 345 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 346 */ 347 val wfi = Bool() 348 } 349 val virtualInst = new Bundle { 350 /** 351 * illegal sfence.vma, svinval.vma 352 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 353 */ 354 val sfenceVMA = Bool() 355 356 /** 357 * illegal sfence.w.inval sfence.inval.ir 358 * raise EX_VI when isModeVU 359 */ 360 val sfencePart = Bool() 361 362 /** 363 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 364 * raise EX_VI when isModeVS || isModeVU 365 */ 366 val hfence = Bool() 367 368 /** 369 * illegal hlv, hlvx, and hsv 370 * raise EX_VI when isModeVS || isModeVU 371 */ 372 val hlsv = Bool() 373 374 /** 375 * illegal wfi 376 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 377 */ 378 val wfi = Bool() 379 } 380}