1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.frontend.FtqPtr 19 20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 21 with HasCircularQueuePtrHelper with HasCriticalErrors 22{ 23 val csrIn = io.csrio.get 24 val csrOut = io.csrio.get 25 val csrToDecode = io.csrToDecode.get 26 27 val setFsDirty = csrIn.fpu.dirty_fs 28 val setFflags = csrIn.fpu.fflags 29 30 val setVsDirty = csrIn.vpu.dirty_vs 31 val setVstart = csrIn.vpu.set_vstart 32 val setVtype = csrIn.vpu.set_vtype 33 val setVxsat = csrIn.vpu.set_vxsat 34 val vlFromPreg = csrIn.vpu.vl 35 36 val flushPipe = Wire(Bool()) 37 val flush = io.flush.valid 38 39 /** Alias of input signals */ 40 val (valid, src1, imm, func) = ( 41 io.in.valid, 42 io.in.bits.data.src(0), 43 io.in.bits.data.imm(Imm_Z().len - 1, 0), 44 io.in.bits.ctrl.fuOpType 45 ) 46 47 // split imm/src1/rd from IMM_Z: src1/rd for tval 48 val addr = Imm_Z().getCSRAddr(imm) 49 val rd = Imm_Z().getRD(imm) 50 val rs1 = Imm_Z().getRS1(imm) 51 val imm5 = Imm_Z().getImm5(imm) 52 val csri = ZeroExt(imm5, XLEN) 53 54 import CSRConst._ 55 56 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 57 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 58 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 59 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 60 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 61 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 62 private val isWfi = CSROpType.isWfi(func) 63 private val isCSRAcc = CSROpType.isCsrAccess(func) 64 65 val csrMod = Module(new NewCSR) 66 val trapInstMod = Module(new TrapInstMod) 67 val trapTvalMod = Module(new TrapTvalMod) 68 69 private val privState = csrMod.io.status.privState 70 // The real reg value in CSR, with no read mask 71 private val regOut = csrMod.io.out.bits.regOut 72 private val src = Mux(CSROpType.needImm(func), csri, src1) 73 private val wdata = LookupTree(func, Seq( 74 CSROpType.wrt -> src1, 75 CSROpType.set -> (regOut | src1), 76 CSROpType.clr -> (regOut & (~src1).asUInt), 77 CSROpType.wrti -> csri, 78 CSROpType.seti -> (regOut | csri), 79 CSROpType.clri -> (regOut & (~csri).asUInt), 80 )) 81 82 private val csrAccess = valid && CSROpType.isCsrAccess(func) 83 private val csrWen = valid && ( 84 CSROpType.isCSRRW(func) || 85 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 86 ) 87 private val csrRen = valid && ( 88 CSROpType.isCSRRW(func) && rd =/= 0.U || 89 CSROpType.isCSRRSorRC(func) 90 ) 91 92 93 csrMod.io.in match { 94 case in => 95 in.valid := valid 96 in.bits.wen := csrWen 97 in.bits.ren := csrRen 98 in.bits.op := CSROpType.getCSROp(func) 99 in.bits.addr := addr 100 in.bits.src := src 101 in.bits.wdata := wdata 102 in.bits.mret := isMret 103 in.bits.mnret := isMNret 104 in.bits.sret := isSret 105 in.bits.dret := isDret 106 } 107 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 108 csrMod.io.fetchMalTval := trapTvalMod.io.tval 109 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 110 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 111 csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE 112 113 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 114 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 115 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 116 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 117 // Todo: shrink the width of trap vector. 118 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 119 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 120 csrMod.io.fromRob.trap.bits.isFetchBkpt := csrIn.exception.bits.isPcBkpt 121 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 122 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 123 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 124 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 125 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 126 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 127 csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE 128 129 csrMod.io.fromRob.commit.fflags := setFflags 130 csrMod.io.fromRob.commit.fsDirty := setFsDirty 131 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 132 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 133 csrMod.io.fromRob.commit.vsDirty := setVsDirty 134 csrMod.io.fromRob.commit.vstart := setVstart 135 csrMod.io.fromRob.commit.vl := vlFromPreg 136 // Todo: correct vtype 137 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 138 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 139 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 140 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 141 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 142 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 143 144 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 145 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 146 147 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 148 149 csrMod.io.fromVecExcpMod.busy := io.csrin.get.fromVecExcpMod.busy 150 151 csrMod.io.perf := csrIn.perf 152 153 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 154 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 155 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 156 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 157 csrMod.platformIRP.STIP := false.B 158 csrMod.platformIRP.VSEIP := false.B // Todo 159 csrMod.platformIRP.VSTIP := false.B // Todo 160 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 161 csrMod.nonMaskableIRP.NMI_43 := csrIn.externalInterrupt.nmi.nmi_43 162 csrMod.nonMaskableIRP.NMI_31 := csrIn.externalInterrupt.nmi.nmi_31 163 164 csrMod.io.fromTop.hartId := io.csrin.get.hartId 165 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 166 csrMod.io.fromTop.criticalErrorState := io.csrin.get.criticalErrorState 167 private val csrModOutValid = csrMod.io.out.valid 168 private val csrModOut = csrMod.io.out.bits 169 170 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 171 trapInstMod.io.fromRob.flush.valid := io.flush.valid 172 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 173 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 174 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 175 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 176 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 177 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 178 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 179 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 180 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 181 case t => 182 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 183 }) 184 185 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 186 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 187 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 188 trapTvalMod.io.fromCtrlBlock.flush := io.flush 189 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 190 191 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 192 imsic.i.hartId := io.csrin.get.hartId 193 imsic.i.msiInfo := io.csrin.get.msiInfo 194 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 195 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 196 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 197 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 198 imsic.i.csr.vgein := csrMod.toAIA.vgein 199 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 200 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 201 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 202 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 203 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 204 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 205 206 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 207 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 208 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 209 csrMod.fromAIA.meip := imsic.o.meip 210 csrMod.fromAIA.seip := imsic.o.seip 211 csrMod.fromAIA.vseip := imsic.o.vseip 212 csrMod.fromAIA.mtopei := imsic.o.mtopei 213 csrMod.fromAIA.stopei := imsic.o.stopei 214 csrMod.fromAIA.vstopei := imsic.o.vstopei 215 216 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 217 218 exceptionVec(EX_BP ) := DataHoldBypass(isEbreak, false.B, io.in.fire) 219 exceptionVec(EX_MCALL ) := DataHoldBypass(isEcall && privState.isModeM, false.B, io.in.fire) 220 exceptionVec(EX_HSCALL) := DataHoldBypass(isEcall && privState.isModeHS, false.B, io.in.fire) 221 exceptionVec(EX_VSCALL) := DataHoldBypass(isEcall && privState.isModeVS, false.B, io.in.fire) 222 exceptionVec(EX_UCALL ) := DataHoldBypass(isEcall && privState.isModeHUorVU, false.B, io.in.fire) 223 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 224 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 225 226 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 227 228 flushPipe := csrMod.io.out.bits.flushPipe 229 230 // tlb 231 val tlb = Wire(new TlbCsrBundle) 232 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 233 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 234 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 235 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 236 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 237 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 238 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 239 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 240 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 241 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 242 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 243 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 244 245 // expose several csr bits for tlb 246 tlb.priv.mxr := csrMod.io.tlb.mxr 247 tlb.priv.sum := csrMod.io.tlb.sum 248 tlb.priv.vmxr := csrMod.io.tlb.vmxr 249 tlb.priv.vsum := csrMod.io.tlb.vsum 250 tlb.priv.spvp := csrMod.io.tlb.spvp 251 tlb.priv.virt := csrMod.io.tlb.dvirt 252 tlb.priv.imode := csrMod.io.tlb.imode 253 tlb.priv.dmode := csrMod.io.tlb.dmode 254 255 // Svpbmt extension enable 256 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 257 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 258 259 // pointer masking extension 260 tlb.pmm := csrMod.io.tlb.pmm 261 262 /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */ 263 io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR 264 io.out.valid := csrModOutValid 265 io.out.bits.ctrl.exceptionVec.get := exceptionVec 266 io.out.bits.ctrl.flushPipe.get := flushPipe 267 io.out.bits.res.data := csrMod.io.out.bits.rData 268 269 /** initialize NewCSR's io_out_ready from wrapper's io */ 270 csrMod.io.out.ready := io.out.ready 271 272 io.out.bits.res.redirect.get.valid := io.out.valid && RegEnable(isXRet, false.B, io.in.fire) 273 val redirect = io.out.bits.res.redirect.get.bits 274 redirect := 0.U.asTypeOf(redirect) 275 redirect.level := RedirectLevel.flushAfter 276 redirect.robIdx := RegEnable(io.in.bits.ctrl.robIdx, io.in.fire) 277 redirect.ftqIdx := RegEnable(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 278 redirect.ftqOffset := RegEnable(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 279 redirect.cfiUpdate.predTaken := true.B 280 redirect.cfiUpdate.taken := true.B 281 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 282 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 283 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 284 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 285 // Only mispred will send redirect to frontend 286 redirect.cfiUpdate.isMisPred := true.B 287 288 connectNonPipedCtrlSingal 289 290 override val criticalErrors = csrMod.getCriticalErrors 291 generateCriticalErrors() 292 293 // Todo: summerize all difftest skip condition 294 csrOut.isPerfCnt := io.out.valid && csrMod.io.out.bits.isPerfCnt && RegEnable(func =/= CSROpType.jmp, false.B, io.in.fire) 295 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 296 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 297 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 298 299 csrOut.isXRet := isXRet 300 301 csrOut.trapTarget := csrMod.io.out.bits.targetPc 302 csrOut.interrupt := csrMod.io.status.interrupt 303 csrOut.wfi_event := csrMod.io.status.wfiEvent 304 305 csrOut.tlb := tlb 306 307 csrOut.debugMode := csrMod.io.status.debugMode 308 309 csrOut.traceCSR := csrMod.io.status.traceCSR 310 311 csrOut.customCtrl match { 312 case custom => 313 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 314 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 315 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 316 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 317 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 318 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 319 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 320 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 321 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 322 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 323 // ICache 324 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 325 // Load violation predictor 326 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 327 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 328 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 329 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 330 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 331 // Branch predictor 332 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 333 // Memory Block 334 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 335 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 336 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 337 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 338 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 339 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 340 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 341 // Rename 342 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 343 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 344 // distribute csr write signal 345 // write to frontend and memory 346 custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal 347 custom.distribute_csr.w.bits.addr := addr 348 custom.distribute_csr.w.bits.data := wdata 349 // rename single step 350 custom.singlestep := csrMod.io.status.singleStepFlag 351 // trigger 352 custom.frontend_trigger := csrMod.io.status.frontendTrigger 353 custom.mem_trigger := csrMod.io.status.memTrigger 354 // virtual mode 355 custom.virtMode := csrMod.io.status.privState.V.asBool 356 // xstatus.fs field is off 357 custom.fsIsOff := csrMod.io.toDecode.illegalInst.fsIsOff 358 } 359 360 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 361 csrOut.criticalErrorState := csrMod.io.status.criticalErrorState 362 363 csrToDecode := csrMod.io.toDecode 364} 365 366class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 367 val hartId = Input(UInt(8.W)) 368 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 369 val criticalErrorState = Input(Bool()) 370 val clintTime = Input(ValidIO(UInt(64.W))) 371 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 372 val fromVecExcpMod = Input(new Bundle { 373 val busy = Bool() 374 }) 375} 376 377class CSRToDecode(implicit p: Parameters) extends XSBundle { 378 val illegalInst = new Bundle { 379 /** 380 * illegal sfence.vma, sinval.vma 381 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 382 */ 383 val sfenceVMA = Bool() 384 385 /** 386 * illegal sfence.w.inval sfence.inval.ir 387 * raise EX_II when isModeHU 388 */ 389 val sfencePart = Bool() 390 391 /** 392 * illegal hfence.gvma, hinval.gvma 393 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 394 * the condition is the same as sfenceVMA 395 */ 396 val hfenceGVMA = Bool() 397 398 /** 399 * illegal hfence.vvma, hinval.vvma 400 * raise EX_II when isModeHU 401 */ 402 val hfenceVVMA = Bool() 403 404 /** 405 * illegal hlv, hlvx, and hsv 406 * raise EX_II when isModeHU && hstatus.HU=0 407 */ 408 val hlsv = Bool() 409 410 /** 411 * decode all fp inst or all vecfp inst 412 * raise EX_II when FS=Off 413 */ 414 val fsIsOff = Bool() 415 416 /** 417 * decode all vec inst 418 * raise EX_II when VS=Off 419 */ 420 val vsIsOff = Bool() 421 422 /** 423 * illegal wfi 424 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 425 */ 426 val wfi = Bool() 427 428 /** 429 * frm reserved 430 * raise EX_II when frm.data > 4 431 */ 432 val frm = Bool() 433 434 /** 435 * illegal CBO.ZERO 436 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE 437 */ 438 val cboZ = Bool() 439 440 /** 441 * illegal CBO.CLEAN/FLUSH 442 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE 443 */ 444 val cboCF = Bool() 445 446 /** 447 * illegal CBO.INVAL 448 * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off 449 */ 450 val cboI = Bool() 451 } 452 453 val virtualInst = new Bundle { 454 /** 455 * illegal sfence.vma, svinval.vma 456 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 457 */ 458 val sfenceVMA = Bool() 459 460 /** 461 * illegal sfence.w.inval sfence.inval.ir 462 * raise EX_VI when isModeVU 463 */ 464 val sfencePart = Bool() 465 466 /** 467 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 468 * raise EX_VI when isModeVS || isModeVU 469 */ 470 val hfence = Bool() 471 472 /** 473 * illegal hlv, hlvx, and hsv 474 * raise EX_VI when isModeVS || isModeVU 475 */ 476 val hlsv = Bool() 477 478 /** 479 * illegal wfi 480 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 481 */ 482 val wfi = Bool() 483 484 /** 485 * illegal CBO.ZERO 486 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE)) 487 */ 488 val cboZ = Bool() 489 490 /** 491 * illegal CBO.CLEAN/FLUSH 492 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE)) 493 */ 494 val cboCF = Bool() 495 496 /** 497 * illegal CBO.INVAL <br/> 498 * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/> 499 * isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/> 500 * isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/> 501 * ) <br/> 502 */ 503 val cboI = Bool() 504 } 505 506 val special = new Bundle { 507 /** 508 * execute CBO.INVAL and perform flush operation when <br/> 509 * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/> 510 * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 511 * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/> 512 * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 513 */ 514 val cboI2F = Bool() 515 } 516}