1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.backend.rob.RobPtr 19import xiangshan.frontend.FtqPtr 20 21class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 22 with HasCircularQueuePtrHelper with HasCriticalErrors 23{ 24 val csrIn = io.csrio.get 25 val csrOut = io.csrio.get 26 val csrToDecode = io.csrToDecode.get 27 28 val setFsDirty = csrIn.fpu.dirty_fs 29 val setFflags = csrIn.fpu.fflags 30 31 val setVsDirty = csrIn.vpu.dirty_vs 32 val setVstart = csrIn.vpu.set_vstart 33 val setVtype = csrIn.vpu.set_vtype 34 val setVxsat = csrIn.vpu.set_vxsat 35 val vlFromPreg = csrIn.vpu.vl 36 37 val flushPipe = Wire(Bool()) 38 val flush = io.flush.valid 39 40 /** Alias of input signals */ 41 val (valid, src1, imm, func) = ( 42 io.in.valid, 43 io.in.bits.data.src(0), 44 io.in.bits.data.imm(Imm_Z().len - 1, 0), 45 io.in.bits.ctrl.fuOpType 46 ) 47 48 // split imm/src1/rd from IMM_Z: src1/rd for tval 49 val addr = Imm_Z().getCSRAddr(imm) 50 val rd = Imm_Z().getRD(imm) 51 val rs1 = Imm_Z().getRS1(imm) 52 val imm5 = Imm_Z().getImm5(imm) 53 val csri = ZeroExt(imm5, XLEN) 54 55 import CSRConst._ 56 57 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 58 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 59 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 60 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 61 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 62 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 63 private val isWfi = CSROpType.isWfi(func) 64 private val isCSRAcc = CSROpType.isCsrAccess(func) 65 66 val csrMod = Module(new NewCSR) 67 val trapInstMod = Module(new TrapInstMod) 68 val trapTvalMod = Module(new TrapTvalMod) 69 70 private val privState = csrMod.io.status.privState 71 // The real reg value in CSR, with no read mask 72 private val regOut = csrMod.io.out.bits.regOut 73 private val src = Mux(CSROpType.needImm(func), csri, src1) 74 private val wdata = LookupTree(func, Seq( 75 CSROpType.wrt -> src1, 76 CSROpType.set -> (regOut | src1), 77 CSROpType.clr -> (regOut & (~src1).asUInt), 78 CSROpType.wrti -> csri, 79 CSROpType.seti -> (regOut | csri), 80 CSROpType.clri -> (regOut & (~csri).asUInt), 81 )) 82 83 private val csrAccess = valid && CSROpType.isCsrAccess(func) 84 private val csrWen = valid && ( 85 CSROpType.isCSRRW(func) || 86 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 87 ) 88 private val csrRen = valid && ( 89 CSROpType.isCSRRW(func) && rd =/= 0.U || 90 CSROpType.isCSRRSorRC(func) 91 ) 92 93 private val robIdxReg = RegEnable(io.in.bits.ctrl.robIdx, io.in.fire) 94 private val thisRobIdx = Wire(new RobPtr) 95 when (io.in.valid) { 96 thisRobIdx := io.in.bits.ctrl.robIdx 97 }.otherwise { 98 thisRobIdx := robIdxReg 99 } 100 private val redirectFlush = thisRobIdx.needFlush(io.flush) 101 102 csrMod.io.in match { 103 case in => 104 in.valid := valid 105 in.bits.wen := csrWen 106 in.bits.ren := csrRen 107 in.bits.op := CSROpType.getCSROp(func) 108 in.bits.addr := addr 109 in.bits.src := src 110 in.bits.wdata := wdata 111 in.bits.mret := isMret 112 in.bits.mnret := isMNret 113 in.bits.sret := isSret 114 in.bits.dret := isDret 115 in.bits.redirectFlush := redirectFlush 116 } 117 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 118 csrMod.io.fetchMalTval := trapTvalMod.io.tval 119 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 120 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 121 csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE 122 123 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 124 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 125 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 126 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 127 // Todo: shrink the width of trap vector. 128 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 129 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 130 csrMod.io.fromRob.trap.bits.isFetchBkpt := csrIn.exception.bits.isPcBkpt 131 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 132 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 133 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 134 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 135 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 136 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 137 csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE 138 139 csrMod.io.fromRob.commit.fflags := setFflags 140 csrMod.io.fromRob.commit.fsDirty := setFsDirty 141 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 142 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 143 csrMod.io.fromRob.commit.vsDirty := setVsDirty 144 csrMod.io.fromRob.commit.vstart := setVstart 145 csrMod.io.fromRob.commit.vl := vlFromPreg 146 // Todo: correct vtype 147 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 148 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 149 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 150 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 151 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 152 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 153 154 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 155 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 156 157 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 158 159 csrMod.io.fromVecExcpMod.busy := io.csrin.get.fromVecExcpMod.busy 160 161 csrMod.io.perf := csrIn.perf 162 163 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 164 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 165 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 166 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 167 csrMod.platformIRP.STIP := false.B 168 csrMod.platformIRP.VSEIP := false.B // Todo 169 csrMod.platformIRP.VSTIP := false.B // Todo 170 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 171 csrMod.nonMaskableIRP.NMI_43 := csrIn.externalInterrupt.nmi.nmi_43 172 csrMod.nonMaskableIRP.NMI_31 := csrIn.externalInterrupt.nmi.nmi_31 173 174 csrMod.io.fromTop.hartId := io.csrin.get.hartId 175 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 176 csrMod.io.fromTop.criticalErrorState := io.csrin.get.criticalErrorState 177 private val csrModOutValid = csrMod.io.out.valid 178 private val csrModOut = csrMod.io.out.bits 179 180 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 181 trapInstMod.io.fromRob.flush.valid := io.flush.valid 182 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 183 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 184 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 185 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 186 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 187 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 188 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 189 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 190 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 191 case t => 192 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 193 }) 194 195 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 196 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 197 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 198 trapTvalMod.io.fromCtrlBlock.flush := io.flush 199 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 200 201 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 202 imsic.i.hartId := io.csrin.get.hartId 203 imsic.i.msiInfo := io.csrin.get.msiInfo 204 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 205 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 206 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 207 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 208 imsic.i.csr.vgein := csrMod.toAIA.vgein 209 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 210 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 211 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 212 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 213 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 214 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 215 216 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 217 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 218 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 219 csrMod.fromAIA.meip := imsic.o.meip 220 csrMod.fromAIA.seip := imsic.o.seip 221 csrMod.fromAIA.vseip := imsic.o.vseip 222 csrMod.fromAIA.mtopei := imsic.o.mtopei 223 csrMod.fromAIA.stopei := imsic.o.stopei 224 csrMod.fromAIA.vstopei := imsic.o.vstopei 225 226 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 227 228 exceptionVec(EX_BP ) := DataHoldBypass(isEbreak, false.B, io.in.fire) 229 exceptionVec(EX_MCALL ) := DataHoldBypass(isEcall && privState.isModeM, false.B, io.in.fire) 230 exceptionVec(EX_HSCALL) := DataHoldBypass(isEcall && privState.isModeHS, false.B, io.in.fire) 231 exceptionVec(EX_VSCALL) := DataHoldBypass(isEcall && privState.isModeVS, false.B, io.in.fire) 232 exceptionVec(EX_UCALL ) := DataHoldBypass(isEcall && privState.isModeHUorVU, false.B, io.in.fire) 233 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 234 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 235 236 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 237 238 flushPipe := csrMod.io.out.bits.flushPipe 239 240 // tlb 241 val tlb = Wire(new TlbCsrBundle) 242 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 243 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 244 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 245 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 246 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 247 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 248 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 249 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 250 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 251 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 252 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 253 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 254 255 // expose several csr bits for tlb 256 tlb.priv.mxr := csrMod.io.tlb.mxr 257 tlb.priv.sum := csrMod.io.tlb.sum 258 tlb.priv.vmxr := csrMod.io.tlb.vmxr 259 tlb.priv.vsum := csrMod.io.tlb.vsum 260 tlb.priv.spvp := csrMod.io.tlb.spvp 261 tlb.priv.virt := csrMod.io.tlb.dvirt 262 tlb.priv.imode := csrMod.io.tlb.imode 263 tlb.priv.dmode := csrMod.io.tlb.dmode 264 265 // Svpbmt extension enable 266 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 267 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 268 269 // pointer masking extension 270 tlb.pmm := csrMod.io.tlb.pmm 271 272 /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */ 273 io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR 274 io.out.valid := csrModOutValid 275 io.out.bits.ctrl.exceptionVec.get := exceptionVec 276 io.out.bits.ctrl.flushPipe.get := flushPipe 277 io.out.bits.res.data := csrMod.io.out.bits.rData 278 279 /** initialize NewCSR's io_out_ready from wrapper's io */ 280 csrMod.io.out.ready := io.out.ready 281 282 io.out.bits.res.redirect.get.valid := io.out.valid && RegEnable(isXRet, false.B, io.in.fire) 283 val redirect = io.out.bits.res.redirect.get.bits 284 redirect := 0.U.asTypeOf(redirect) 285 redirect.level := RedirectLevel.flushAfter 286 redirect.robIdx := robIdxReg 287 redirect.ftqIdx := RegEnable(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 288 redirect.ftqOffset := RegEnable(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 289 redirect.cfiUpdate.predTaken := true.B 290 redirect.cfiUpdate.taken := true.B 291 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 292 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 293 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 294 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 295 // Only mispred will send redirect to frontend 296 redirect.cfiUpdate.isMisPred := true.B 297 298 connectNonPipedCtrlSingal 299 300 override val criticalErrors = csrMod.getCriticalErrors 301 generateCriticalErrors() 302 303 // Todo: summerize all difftest skip condition 304 csrOut.isPerfCnt := io.out.valid && csrMod.io.out.bits.isPerfCnt && RegEnable(func =/= CSROpType.jmp, false.B, io.in.fire) 305 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 306 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 307 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 308 309 csrOut.isXRet := isXRet 310 311 csrOut.trapTarget := csrMod.io.out.bits.targetPc 312 csrOut.interrupt := csrMod.io.status.interrupt 313 csrOut.wfi_event := csrMod.io.status.wfiEvent 314 315 csrOut.tlb := tlb 316 317 csrOut.debugMode := csrMod.io.status.debugMode 318 319 csrOut.traceCSR := csrMod.io.status.traceCSR 320 321 csrOut.customCtrl match { 322 case custom => 323 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 324 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 325 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 326 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 327 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 328 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 329 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 330 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 331 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 332 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 333 // ICache 334 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 335 // Load violation predictor 336 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 337 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 338 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 339 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 340 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 341 // Branch predictor 342 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 343 // Memory Block 344 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 345 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 346 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 347 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 348 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 349 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 350 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 351 // Rename 352 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 353 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 354 // distribute csr write signal 355 // write to frontend and memory 356 custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal 357 custom.distribute_csr.w.bits.addr := addr 358 custom.distribute_csr.w.bits.data := wdata 359 // rename single step 360 custom.singlestep := csrMod.io.status.singleStepFlag 361 // trigger 362 custom.frontend_trigger := csrMod.io.status.frontendTrigger 363 custom.mem_trigger := csrMod.io.status.memTrigger 364 // virtual mode 365 custom.virtMode := csrMod.io.status.privState.V.asBool 366 // xstatus.fs field is off 367 custom.fsIsOff := csrMod.io.toDecode.illegalInst.fsIsOff 368 } 369 370 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 371 csrOut.criticalErrorState := csrMod.io.status.criticalErrorState 372 373 csrToDecode := csrMod.io.toDecode 374} 375 376class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 377 val hartId = Input(UInt(8.W)) 378 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 379 val criticalErrorState = Input(Bool()) 380 val clintTime = Input(ValidIO(UInt(64.W))) 381 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 382 val fromVecExcpMod = Input(new Bundle { 383 val busy = Bool() 384 }) 385} 386 387class CSRToDecode(implicit p: Parameters) extends XSBundle { 388 val illegalInst = new Bundle { 389 /** 390 * illegal sfence.vma, sinval.vma 391 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 392 */ 393 val sfenceVMA = Bool() 394 395 /** 396 * illegal sfence.w.inval sfence.inval.ir 397 * raise EX_II when isModeHU 398 */ 399 val sfencePart = Bool() 400 401 /** 402 * illegal hfence.gvma, hinval.gvma 403 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 404 * the condition is the same as sfenceVMA 405 */ 406 val hfenceGVMA = Bool() 407 408 /** 409 * illegal hfence.vvma, hinval.vvma 410 * raise EX_II when isModeHU 411 */ 412 val hfenceVVMA = Bool() 413 414 /** 415 * illegal hlv, hlvx, and hsv 416 * raise EX_II when isModeHU && hstatus.HU=0 417 */ 418 val hlsv = Bool() 419 420 /** 421 * decode all fp inst or all vecfp inst 422 * raise EX_II when FS=Off 423 */ 424 val fsIsOff = Bool() 425 426 /** 427 * decode all vec inst 428 * raise EX_II when VS=Off 429 */ 430 val vsIsOff = Bool() 431 432 /** 433 * illegal wfi 434 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 435 */ 436 val wfi = Bool() 437 438 /** 439 * frm reserved 440 * raise EX_II when frm.data > 4 441 */ 442 val frm = Bool() 443 444 /** 445 * illegal CBO.ZERO 446 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE 447 */ 448 val cboZ = Bool() 449 450 /** 451 * illegal CBO.CLEAN/FLUSH 452 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE 453 */ 454 val cboCF = Bool() 455 456 /** 457 * illegal CBO.INVAL 458 * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off 459 */ 460 val cboI = Bool() 461 } 462 463 val virtualInst = new Bundle { 464 /** 465 * illegal sfence.vma, svinval.vma 466 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 467 */ 468 val sfenceVMA = Bool() 469 470 /** 471 * illegal sfence.w.inval sfence.inval.ir 472 * raise EX_VI when isModeVU 473 */ 474 val sfencePart = Bool() 475 476 /** 477 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 478 * raise EX_VI when isModeVS || isModeVU 479 */ 480 val hfence = Bool() 481 482 /** 483 * illegal hlv, hlvx, and hsv 484 * raise EX_VI when isModeVS || isModeVU 485 */ 486 val hlsv = Bool() 487 488 /** 489 * illegal wfi 490 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 491 */ 492 val wfi = Bool() 493 494 /** 495 * illegal CBO.ZERO 496 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE)) 497 */ 498 val cboZ = Bool() 499 500 /** 501 * illegal CBO.CLEAN/FLUSH 502 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE)) 503 */ 504 val cboCF = Bool() 505 506 /** 507 * illegal CBO.INVAL <br/> 508 * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/> 509 * isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/> 510 * isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/> 511 * ) <br/> 512 */ 513 val cboI = Bool() 514 } 515 516 val special = new Bundle { 517 /** 518 * execute CBO.INVAL and perform flush operation when <br/> 519 * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/> 520 * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 521 * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/> 522 * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 523 */ 524 val cboI2F = Bool() 525 } 526}