1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.backend.rob.RobPtr 19import xiangshan.frontend.FtqPtr 20 21class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 22 with HasCircularQueuePtrHelper with HasCriticalErrors 23{ 24 val csrIn = io.csrio.get 25 val csrOut = io.csrio.get 26 val csrToDecode = io.csrToDecode.get 27 28 val setFsDirty = csrIn.fpu.dirty_fs 29 val setFflags = csrIn.fpu.fflags 30 31 val setVsDirty = csrIn.vpu.dirty_vs 32 val setVstart = csrIn.vpu.set_vstart 33 val setVtype = csrIn.vpu.set_vtype 34 val setVxsat = csrIn.vpu.set_vxsat 35 val vlFromPreg = csrIn.vpu.vl 36 37 val flushPipe = Wire(Bool()) 38 val flush = io.flush.valid 39 40 /** Alias of input signals */ 41 val (valid, src1, imm, func) = ( 42 io.in.valid, 43 io.in.bits.data.src(0), 44 io.in.bits.data.imm(Imm_Z().len - 1, 0), 45 io.in.bits.ctrl.fuOpType 46 ) 47 48 // split imm/src1/rd from IMM_Z: src1/rd for tval 49 val addr = Imm_Z().getCSRAddr(imm) 50 val rd = Imm_Z().getRD(imm) 51 val rs1 = Imm_Z().getRS1(imm) 52 val imm5 = Imm_Z().getImm5(imm) 53 val csri = ZeroExt(imm5, XLEN) 54 55 import CSRConst._ 56 57 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 58 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 59 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 60 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 61 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 62 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 63 private val isWfi = CSROpType.isWfi(func) 64 private val isCSRAcc = CSROpType.isCsrAccess(func) 65 66 val csrMod = Module(new NewCSR) 67 val trapInstMod = Module(new TrapInstMod) 68 val trapTvalMod = Module(new TrapTvalMod) 69 70 private val privState = csrMod.io.status.privState 71 // The real reg value in CSR, with no read mask 72 private val regOut = csrMod.io.out.bits.regOut 73 private val src = Mux(CSROpType.needImm(func), csri, src1) 74 private val wdata = LookupTree(func, Seq( 75 CSROpType.wrt -> src1, 76 CSROpType.set -> (regOut | src1), 77 CSROpType.clr -> (regOut & (~src1).asUInt), 78 CSROpType.wrti -> csri, 79 CSROpType.seti -> (regOut | csri), 80 CSROpType.clri -> (regOut & (~csri).asUInt), 81 )) 82 83 private val csrAccess = valid && CSROpType.isCsrAccess(func) 84 private val csrWen = valid && ( 85 CSROpType.isCSRRW(func) || 86 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 87 ) 88 private val csrRen = valid && ( 89 CSROpType.isCSRRW(func) && rd =/= 0.U || 90 CSROpType.isCSRRSorRC(func) 91 ) 92 93 private val waddrReg = RegEnable(addr, 0.U(12.W), io.in.fire) 94 private val wdataReg = RegEnable(wdata, 0.U(64.W), io.in.fire) 95 96 private val robIdxReg = RegEnable(io.in.bits.ctrl.robIdx, io.in.fire) 97 private val thisRobIdx = Wire(new RobPtr) 98 when (io.in.valid) { 99 thisRobIdx := io.in.bits.ctrl.robIdx 100 }.otherwise { 101 thisRobIdx := robIdxReg 102 } 103 private val redirectFlush = thisRobIdx.needFlush(io.flush) 104 105 csrMod.io.in match { 106 case in => 107 in.valid := valid 108 in.bits.wen := csrWen 109 in.bits.ren := csrRen 110 in.bits.op := CSROpType.getCSROp(func) 111 in.bits.addr := addr 112 in.bits.src := src 113 in.bits.wdata := wdataReg 114 in.bits.mret := isMret 115 in.bits.mnret := isMNret 116 in.bits.sret := isSret 117 in.bits.dret := isDret 118 in.bits.redirectFlush := redirectFlush 119 } 120 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 121 csrMod.io.fetchMalTval := trapTvalMod.io.tval 122 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 123 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 124 csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE 125 126 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 127 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 128 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 129 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 130 // Todo: shrink the width of trap vector. 131 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 132 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 133 csrMod.io.fromRob.trap.bits.isFetchBkpt := csrIn.exception.bits.isPcBkpt 134 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 135 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 136 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 137 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 138 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 139 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 140 csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE 141 142 csrMod.io.fromRob.commit.fflags := setFflags 143 csrMod.io.fromRob.commit.fsDirty := setFsDirty 144 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 145 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 146 csrMod.io.fromRob.commit.vsDirty := setVsDirty 147 csrMod.io.fromRob.commit.vstart := setVstart 148 csrMod.io.fromRob.commit.vl := vlFromPreg 149 // Todo: correct vtype 150 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 151 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 152 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 153 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 154 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 155 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 156 157 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 158 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 159 160 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 161 162 csrMod.io.fromVecExcpMod.busy := io.csrin.get.fromVecExcpMod.busy 163 164 csrMod.io.perf := csrIn.perf 165 166 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 167 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 168 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 169 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 170 csrMod.platformIRP.STIP := false.B 171 csrMod.platformIRP.VSEIP := false.B // Todo 172 csrMod.platformIRP.VSTIP := false.B // Todo 173 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 174 csrMod.nonMaskableIRP.NMI_43 := csrIn.externalInterrupt.nmi.nmi_43 175 csrMod.nonMaskableIRP.NMI_31 := csrIn.externalInterrupt.nmi.nmi_31 176 177 csrMod.io.fromTop.hartId := io.csrin.get.hartId 178 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 179 csrMod.io.fromTop.l2FlushDone := io.csrin.get.l2FlushDone 180 csrMod.io.fromTop.criticalErrorState := io.csrin.get.criticalErrorState 181 private val csrModOutValid = csrMod.io.out.valid 182 private val csrModOut = csrMod.io.out.bits 183 184 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 185 trapInstMod.io.fromRob.flush.valid := io.flush.valid 186 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 187 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 188 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 189 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 190 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 191 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 192 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 193 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 194 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 195 case t => 196 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 197 }) 198 199 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 200 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 201 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 202 trapTvalMod.io.fromCtrlBlock.flush := io.flush 203 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 204 205 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 206 imsic.i.hartId := io.csrin.get.hartId 207 imsic.i.msiInfo := io.csrin.get.msiInfo 208 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 209 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 210 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 211 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 212 imsic.i.csr.vgein := csrMod.toAIA.vgein 213 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 214 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 215 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 216 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 217 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 218 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 219 220 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 221 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 222 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 223 csrMod.fromAIA.meip := imsic.o.meip 224 csrMod.fromAIA.seip := imsic.o.seip 225 csrMod.fromAIA.vseip := imsic.o.vseip 226 csrMod.fromAIA.mtopei := imsic.o.mtopei 227 csrMod.fromAIA.stopei := imsic.o.stopei 228 csrMod.fromAIA.vstopei := imsic.o.vstopei 229 230 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 231 232 exceptionVec(EX_BP ) := DataHoldBypass(isEbreak, false.B, io.in.fire) 233 exceptionVec(EX_MCALL ) := DataHoldBypass(isEcall && privState.isModeM, false.B, io.in.fire) 234 exceptionVec(EX_HSCALL) := DataHoldBypass(isEcall && privState.isModeHS, false.B, io.in.fire) 235 exceptionVec(EX_VSCALL) := DataHoldBypass(isEcall && privState.isModeVS, false.B, io.in.fire) 236 exceptionVec(EX_UCALL ) := DataHoldBypass(isEcall && privState.isModeHUorVU, false.B, io.in.fire) 237 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 238 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 239 240 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 241 242 flushPipe := csrMod.io.out.bits.flushPipe 243 244 // tlb 245 val tlb = Wire(new TlbCsrBundle) 246 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 247 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 248 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 249 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 250 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 251 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 252 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 253 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 254 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 255 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 256 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 257 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 258 259 // expose several csr bits for tlb 260 tlb.priv.mxr := csrMod.io.tlb.mxr 261 tlb.priv.sum := csrMod.io.tlb.sum 262 tlb.priv.vmxr := csrMod.io.tlb.vmxr 263 tlb.priv.vsum := csrMod.io.tlb.vsum 264 tlb.priv.spvp := csrMod.io.tlb.spvp 265 tlb.priv.virt := csrMod.io.tlb.dvirt 266 tlb.priv.imode := csrMod.io.tlb.imode 267 tlb.priv.dmode := csrMod.io.tlb.dmode 268 269 // Svpbmt extension enable 270 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 271 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 272 273 // pointer masking extension 274 tlb.pmm := csrMod.io.tlb.pmm 275 276 /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */ 277 io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR 278 io.out.valid := csrModOutValid 279 io.out.bits.ctrl.exceptionVec.get := exceptionVec 280 io.out.bits.ctrl.flushPipe.get := flushPipe 281 io.out.bits.res.data := csrMod.io.out.bits.rData 282 283 /** initialize NewCSR's io_out_ready from wrapper's io */ 284 csrMod.io.out.ready := io.out.ready 285 286 io.out.bits.res.redirect.get.valid := io.out.valid && RegEnable(isXRet, false.B, io.in.fire) 287 val redirect = io.out.bits.res.redirect.get.bits 288 redirect := 0.U.asTypeOf(redirect) 289 redirect.level := RedirectLevel.flushAfter 290 redirect.robIdx := robIdxReg 291 redirect.ftqIdx := RegEnable(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 292 redirect.ftqOffset := RegEnable(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 293 redirect.cfiUpdate.predTaken := true.B 294 redirect.cfiUpdate.taken := true.B 295 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 296 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 297 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 298 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 299 // Only mispred will send redirect to frontend 300 redirect.cfiUpdate.isMisPred := true.B 301 302 connectNonPipedCtrlSingal 303 304 override val criticalErrors = csrMod.getCriticalErrors 305 generateCriticalErrors() 306 307 // Todo: summerize all difftest skip condition 308 csrOut.isPerfCnt := io.out.valid && csrMod.io.out.bits.isPerfCnt && RegEnable(func =/= CSROpType.jmp, false.B, io.in.fire) 309 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 310 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 311 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 312 313 csrOut.isXRet := isXRet 314 315 csrOut.trapTarget := csrMod.io.out.bits.targetPc 316 csrOut.interrupt := csrMod.io.status.interrupt 317 csrOut.wfi_event := csrMod.io.status.wfiEvent 318 319 csrOut.tlb := tlb 320 321 csrOut.debugMode := csrMod.io.status.debugMode 322 323 csrOut.traceCSR := csrMod.io.status.traceCSR 324 325 csrOut.customCtrl match { 326 case custom => 327 custom.pf_ctrl := csrMod.io.status.custom.pf_ctrl 328 // Load violation predictor 329 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 330 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 331 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 332 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 333 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 334 // Branch predictor 335 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 336 // Memory Block 337 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 338 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 339 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 340 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 341 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 342 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 343 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 344 custom.power_down_enable := csrMod.io.status.custom.power_down_enable 345 custom.flush_l2_enable := csrMod.io.status.custom.flush_l2_enable 346 // Rename 347 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 348 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 349 // distribute csr write signal 350 // write to frontend and memory 351 custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal 352 custom.distribute_csr.w.bits.addr := waddrReg 353 custom.distribute_csr.w.bits.data := wdataReg 354 // rename single step 355 custom.singlestep := csrMod.io.status.singleStepFlag 356 // trigger 357 custom.frontend_trigger := csrMod.io.status.frontendTrigger 358 custom.mem_trigger := csrMod.io.status.memTrigger 359 // virtual mode 360 custom.virtMode := csrMod.io.status.privState.V.asBool 361 // xstatus.fs field is off 362 custom.fsIsOff := csrMod.io.toDecode.illegalInst.fsIsOff 363 } 364 365 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 366 csrOut.criticalErrorState := csrMod.io.status.criticalErrorState 367 368 csrToDecode := csrMod.io.toDecode 369} 370 371class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 372 val hartId = Input(UInt(8.W)) 373 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 374 val criticalErrorState = Input(Bool()) 375 val clintTime = Input(ValidIO(UInt(64.W))) 376 val l2FlushDone = Input(Bool()) 377 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 378 val fromVecExcpMod = Input(new Bundle { 379 val busy = Bool() 380 }) 381} 382 383class CSRToDecode(implicit p: Parameters) extends XSBundle { 384 val illegalInst = new Bundle { 385 /** 386 * illegal sfence.vma, sinval.vma 387 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 388 */ 389 val sfenceVMA = Bool() 390 391 /** 392 * illegal sfence.w.inval sfence.inval.ir 393 * raise EX_II when isModeHU 394 */ 395 val sfencePart = Bool() 396 397 /** 398 * illegal hfence.gvma, hinval.gvma 399 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 400 * the condition is the same as sfenceVMA 401 */ 402 val hfenceGVMA = Bool() 403 404 /** 405 * illegal hfence.vvma, hinval.vvma 406 * raise EX_II when isModeHU 407 */ 408 val hfenceVVMA = Bool() 409 410 /** 411 * illegal hlv, hlvx, and hsv 412 * raise EX_II when isModeHU && hstatus.HU=0 413 */ 414 val hlsv = Bool() 415 416 /** 417 * decode all fp inst or all vecfp inst 418 * raise EX_II when FS=Off 419 */ 420 val fsIsOff = Bool() 421 422 /** 423 * decode all vec inst 424 * raise EX_II when VS=Off 425 */ 426 val vsIsOff = Bool() 427 428 /** 429 * illegal wfi 430 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 431 */ 432 val wfi = Bool() 433 434 /** 435 * illegal wrs_nto 436 * raise EX_II when !isModeM && mstatus.TW=1 437 */ 438 val wrs_nto = Bool() 439 440 /** 441 * frm reserved 442 * raise EX_II when frm.data > 4 443 */ 444 val frm = Bool() 445 446 /** 447 * illegal CBO.ZERO 448 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE 449 */ 450 val cboZ = Bool() 451 452 /** 453 * illegal CBO.CLEAN/FLUSH 454 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE 455 */ 456 val cboCF = Bool() 457 458 /** 459 * illegal CBO.INVAL 460 * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off 461 */ 462 val cboI = Bool() 463 } 464 465 val virtualInst = new Bundle { 466 /** 467 * illegal sfence.vma, svinval.vma 468 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 469 */ 470 val sfenceVMA = Bool() 471 472 /** 473 * illegal sfence.w.inval sfence.inval.ir 474 * raise EX_VI when isModeVU 475 */ 476 val sfencePart = Bool() 477 478 /** 479 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 480 * raise EX_VI when isModeVS || isModeVU 481 */ 482 val hfence = Bool() 483 484 /** 485 * illegal hlv, hlvx, and hsv 486 * raise EX_VI when isModeVS || isModeVU 487 */ 488 val hlsv = Bool() 489 490 /** 491 * illegal wfi 492 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 493 */ 494 val wfi = Bool() 495 496 /** 497 * illegal wrs_nto 498 * raise EX_VI when privState.V && mstatus.TW=0 && hstatus.VTW=1 499 */ 500 val wrs_nto = Bool() 501 502 /** 503 * illegal CBO.ZERO 504 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE)) 505 */ 506 val cboZ = Bool() 507 508 /** 509 * illegal CBO.CLEAN/FLUSH 510 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE)) 511 */ 512 val cboCF = Bool() 513 514 /** 515 * illegal CBO.INVAL <br/> 516 * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/> 517 * isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/> 518 * isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/> 519 * ) <br/> 520 */ 521 val cboI = Bool() 522 } 523 524 val special = new Bundle { 525 /** 526 * execute CBO.INVAL and perform flush operation when <br/> 527 * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/> 528 * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 529 * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/> 530 * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 531 */ 532 val cboI2F = Bool() 533 } 534}