xref: /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala (revision db72af19c28fcb9c75ed7bf8385b050efd6f0b23) 
1/****************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 *          http://license.coscl.org.cn/MulanPSL2
9 *
10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13 *
14 * See the Mulan PSL v2 for more details.
15 ****************************************************************************************
16 */
17
18
19package xiangshan.backend.fu.vector
20
21import chipsalliance.rocketchip.config.Parameters
22import chisel3._
23import utils._
24import utility._
25import yunsuan.vector.VectorIntAdder
26import yunsuan.{VipuType, VectorElementFormat}
27import xiangshan.{SrcType, SelImm}
28import xiangshan.backend.fu.FunctionUnit
29import xiangshan.XSCoreParamsKey
30
31class VIPU(implicit p: Parameters) extends FunctionUnit(p(XSCoreParamsKey).VLEN) {
32  XSError(io.in.valid && io.in.bits.uop.ctrl.fuOpType === VipuType.dummy, "VIPU OpType not supported")
33
34  val uop = io.in.bits.uop
35  val ctrl = uop.ctrl
36  val vtype = ctrl.vconfig.vtype
37
38  // TODO: mv VecImmExtractor from exe stage to read rf stage(or forward stage).
39  val imm = VecInit(Seq.fill(VLEN/XLEN)(VecImmExtractor(ctrl.selImm, vtype.vsew, ctrl.imm))).asUInt
40  val src1 = Mux(SrcType.isImm(ctrl.srcType(0)), imm, io.in.bits.src(0))
41  val src2 = io.in.bits.src(1)
42
43  val AdderWidth = XLEN
44  val NumAdder = VLEN / XLEN
45  val adder = Seq.fill(NumAdder)(Module(new VectorIntAdder()))
46  for(i <- 0 until NumAdder) {
47    adder(i).io.in_0 := src1(AdderWidth*(i+1)-1, AdderWidth*i)
48    adder(i).io.in_1 := src2(AdderWidth*(i+1)-1, AdderWidth*i)
49    adder(i).io.int_format := vtype.vsew // TODO
50    adder(i).io.op_code := ctrl.fuOpType
51    adder(i).io.carry_or_borrow_in := DontCare // TODO
52    adder(i).io.uop_index := DontCare // TODO
53  }
54  val adder_result = VecInit(adder.map(_.io.out)).asUInt
55
56  io.out.bits.data := adder_result
57  io.out.bits.uop := io.in.bits.uop
58  io.out.valid := io.in.valid
59  io.in.ready := io.out.ready
60}
61
62object VecImmExtractor {
63  def Imm_OPIVIS(imm: UInt): UInt = {
64    SignExt(imm(4,0), 8)
65  }
66  def Imm_OPIVIU(imm: UInt): UInt = {
67    ZeroExt(imm(4,0), 8)
68  }
69
70  def imm_sew(sew: UInt, imm: UInt): UInt = {
71    val _imm = SignExt(imm(7,0), 64)
72    LookupTree(sew(1,0), List(
73      "b00".U -> VecInit(Seq.fill(8)(_imm(7,0))).asUInt,
74      "b01".U -> VecInit(Seq.fill(4)(_imm(15,0))).asUInt,
75      "b10".U -> VecInit(Seq.fill(2)(_imm(31,0))).asUInt,
76      "b11".U -> _imm(63,0),
77    ))
78  }
79
80  def apply(immType: UInt, sew: UInt, imm: UInt): UInt = {
81    val _imm = Mux(immType === SelImm.IMM_OPIVIS, Imm_OPIVIS(imm), Imm_OPIVIU(imm))
82    imm_sew(sew, _imm(7,0))
83  }
84}
85