130fcc710SZiyue Zhang/**************************************************************************************** 230fcc710SZiyue Zhang * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 330fcc710SZiyue Zhang * Copyright (c) 2020-2021 Peng Cheng Laboratory 430fcc710SZiyue Zhang * 530fcc710SZiyue Zhang * XiangShan is licensed under Mulan PSL v2. 630fcc710SZiyue Zhang * You can use this software according to the terms and conditions of the Mulan PSL v2. 730fcc710SZiyue Zhang * You may obtain a copy of Mulan PSL v2 at: 830fcc710SZiyue Zhang * http://license.coscl.org.cn/MulanPSL2 930fcc710SZiyue Zhang * 1030fcc710SZiyue Zhang * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 1130fcc710SZiyue Zhang * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 1230fcc710SZiyue Zhang * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 1330fcc710SZiyue Zhang * 1430fcc710SZiyue Zhang * See the Mulan PSL v2 for more details. 1530fcc710SZiyue Zhang **************************************************************************************** 1630fcc710SZiyue Zhang */ 1730fcc710SZiyue Zhang 1830fcc710SZiyue Zhang 1930fcc710SZiyue Zhangpackage xiangshan.backend.fu.vector 2030fcc710SZiyue Zhang 2183ba63b3SXuan Huimport org.chipsalliance.cde.config.Parameters 2230fcc710SZiyue Zhangimport chisel3._ 2330fcc710SZiyue Zhangimport chisel3.util._ 2430fcc710SZiyue Zhangimport chiseltest._ 2530fcc710SZiyue Zhangimport org.scalatest.flatspec.AnyFlatSpec 2630fcc710SZiyue Zhangimport org.scalatest.matchers.must.Matchers 2730fcc710SZiyue Zhangimport top.{ArgParser, BaseConfig, DefaultConfig} 2830fcc710SZiyue Zhangimport xiangshan._ 2930fcc710SZiyue Zhangimport xiangshan.backend.fu.vector.Bundles.{Vl} 3030fcc710SZiyue Zhangimport yunsuan.vector._ 3130fcc710SZiyue Zhang 3230fcc710SZiyue Zhangclass Mgtu(vlen: Int)(implicit p: Parameters) extends Module { 3330fcc710SZiyue Zhang val io = IO(new MgtuIO(vlen)) 3430fcc710SZiyue Zhang 3530fcc710SZiyue Zhang val in = io.in 3630fcc710SZiyue Zhang val vd = in.vd 3730fcc710SZiyue Zhang val vl = in.vl 3830fcc710SZiyue Zhang 39*2ada8c08SZiyue Zhang /* 4030fcc710SZiyue Zhang * Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of vta 4130fcc710SZiyue Zhang */ 42*2ada8c08SZiyue Zhang private val vdWithTail = Wire(Vec(vlen, UInt(1.W))) 43*2ada8c08SZiyue Zhang vdWithTail.zipWithIndex.foreach{ case (bit, idx) => 44*2ada8c08SZiyue Zhang bit := Mux(idx.U < vl, vd(idx), 1.U) 45*2ada8c08SZiyue Zhang } 4630fcc710SZiyue Zhang 47*2ada8c08SZiyue Zhang io.out.vd := vdWithTail.asUInt 4830fcc710SZiyue Zhang} 4930fcc710SZiyue Zhang 5030fcc710SZiyue Zhang 5130fcc710SZiyue Zhangclass MgtuIO(vlen: Int)(implicit p: Parameters) extends Bundle { 5230fcc710SZiyue Zhang val in = new Bundle { 5330fcc710SZiyue Zhang val vd = Input(UInt(vlen.W)) 5430fcc710SZiyue Zhang val vl = Input(Vl()) 5530fcc710SZiyue Zhang } 5630fcc710SZiyue Zhang val out = new Bundle { 5730fcc710SZiyue Zhang val vd = Output(UInt(vlen.W)) 5830fcc710SZiyue Zhang } 5930fcc710SZiyue Zhang} 60