1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import utility._ 23import xiangshan._ 24import xiangshan.backend._ 25 26trait HasCSRConst { 27 28 // User Trap Setup 29 val Ustatus = 0x000 30 val Uie = 0x004 31 val Utvec = 0x005 32 33 // User Trap Handling 34 val Uscratch = 0x040 35 val Uepc = 0x041 36 val Ucause = 0x042 37 val Utval = 0x043 38 val Uip = 0x044 39 40 // User Floating-Point CSRs (not implemented) 41 val Fflags = 0x001 42 val Frm = 0x002 43 val Fcsr = 0x003 44 45 // Vector Extension CSRs 46 val Vstart = 0x008 47 val Vxsat = 0x009 48 val Vxrm = 0x00A 49 val Vcsr = 0x00F 50 val Vl = 0xC20 51 val Vtype = 0xC21 52 val Vlenb = 0xC22 53 54 // User Counter/Timers 55 val Cycle = 0xC00 56 val Time = 0xC01 57 val Instret = 0xC02 58 val Hpmcounter3 = 0xC03 59 val Hpmcounter4 = 0xC04 60 val Hpmcounter5 = 0xC05 61 val Hpmcounter6 = 0xC06 62 val Hpmcounter7 = 0xC07 63 val Hpmcounter8 = 0xC08 64 val Hpmcounter9 = 0xC09 65 val Hpmcounter10 = 0xC0A 66 val Hpmcounter11 = 0xC0B 67 val Hpmcounter12 = 0xC0C 68 val Hpmcounter13 = 0xC0D 69 val Hpmcounter14 = 0xC0E 70 val Hpmcounter15 = 0xC0F 71 val Hpmcounter16 = 0xC10 72 val Hpmcounter17 = 0xC11 73 val Hpmcounter18 = 0xC12 74 val Hpmcounter19 = 0xC13 75 val Hpmcounter20 = 0xC14 76 val Hpmcounter21 = 0xC15 77 val Hpmcounter22 = 0xC16 78 val Hpmcounter23 = 0xC17 79 val Hpmcounter24 = 0xC18 80 val Hpmcounter25 = 0xC19 81 val Hpmcounter26 = 0xC1A 82 val Hpmcounter27 = 0xC1B 83 val Hpmcounter28 = 0xC1C 84 val Hpmcounter29 = 0xC1D 85 val Hpmcounter30 = 0xC1E 86 val Hpmcounter31 = 0xC1F 87 88 // Supervisor Trap Setup 89 val Sstatus = 0x100 90 val Sedeleg = 0x102 91 val Sideleg = 0x103 92 val Sie = 0x104 93 val Stvec = 0x105 94 val Scounteren = 0x106 95 96 // Supervisor Configuration 97 val Senvcfg = 0x10A 98 99 // Supervisor Trap Handling 100 val Sscratch = 0x140 101 val Sepc = 0x141 102 val Scause = 0x142 103 val Stval = 0x143 104 val Sip = 0x144 105 106 // Supervisor Protection and Translation 107 val Satp = 0x180 108 109 // Supervisor Custom Read/Write 110 val Sbpctl = 0x5C0 111 val Spfctl = 0x5C1 112 val Slvpredctl = 0x5C2 113 val Smblockctl = 0x5C3 114 val Srnctl = 0x5C4 115 /** 0x5C5-0x5E5 for cache instruction register*/ 116 val Scachebase = 0x5C5 117 118 // Supervisor Custom Read/Write 119 val Sdsid = 0x9C0 120 val Sfetchctl = 0x9e0 121 122 // Hypervisor Trap Setup 123 val Hstatus = 0x600 124 val Hedeleg = 0x602 125 val Hideleg = 0x603 126 val Hie = 0x604 127 val Hcounteren = 0x606 128 val Hgeie = 0x607 129 130 // Hypervisor Trap Handling 131 val Htval = 0x643 132 val Hip = 0x644 133 val Hvip = 0x645 134 val Htinst = 0x64A 135 val Hgeip = 0xE12 136 137 // Hypervisor Configuration 138 val Henvcfg = 0x60A 139 140 // Hypervisor Protection and Translation 141 val Hgatp = 0x680 142 143 //Hypervisor Counter/Timer Virtualization Registers 144 val Htimedelta = 0x605 145 146 // Virtual Supervisor Registers 147 val Vsstatus = 0x200 148 val Vsie = 0x204 149 val Vstvec = 0x205 150 val Vsscratch = 0x240 151 val Vsepc = 0x241 152 val Vscause = 0x242 153 val Vstval = 0x243 154 val Vsip = 0x244 155 val Vsatp = 0x280 156 157 // Machine Information Registers 158 val Mvendorid = 0xF11 159 val Marchid = 0xF12 160 val Mimpid = 0xF13 161 val Mhartid = 0xF14 162 val Mconfigptr = 0xF15 163 164 // Machine Trap Setup 165 val Mstatus = 0x300 166 val Misa = 0x301 167 val Medeleg = 0x302 168 val Mideleg = 0x303 169 val Mie = 0x304 170 val Mtvec = 0x305 171 val Mcounteren = 0x306 172 173 // Machine Trap Handling 174 val Mscratch = 0x340 175 val Mepc = 0x341 176 val Mcause = 0x342 177 val Mtval = 0x343 178 val Mip = 0x344 179 val Mtinst = 0x34A 180 val Mtval2 = 0x34B 181 182 // Machine Configuration 183 val Menvcfg = 0x30A 184 185 // Machine Memory Protection 186 // TBD 187 val PmpcfgBase = 0x3A0 188 val PmpaddrBase = 0x3B0 189 // Machine level PMA 190 val PmacfgBase = 0x7C0 191 val PmaaddrBase = 0x7C8 // 64 entry at most 192 193 // Machine Counter/Timers 194 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 195 // 0xB80 - 0x89F are also used as perfcnt csr 196 val Mcycle = 0xb00 197 val Minstret = 0xb02 198 199 val Mhpmcounter3 = 0xB03 200 val Mhpmcounter4 = 0xB04 201 val Mhpmcounter5 = 0xB05 202 val Mhpmcounter6 = 0xB06 203 val Mhpmcounter7 = 0xB07 204 val Mhpmcounter8 = 0xB08 205 val Mhpmcounter9 = 0xB09 206 val Mhpmcounter10 = 0xB0A 207 val Mhpmcounter11 = 0xB0B 208 val Mhpmcounter12 = 0xB0C 209 val Mhpmcounter13 = 0xB0D 210 val Mhpmcounter14 = 0xB0E 211 val Mhpmcounter15 = 0xB0F 212 val Mhpmcounter16 = 0xB10 213 val Mhpmcounter17 = 0xB11 214 val Mhpmcounter18 = 0xB12 215 val Mhpmcounter19 = 0xB13 216 val Mhpmcounter20 = 0xB14 217 val Mhpmcounter21 = 0xB15 218 val Mhpmcounter22 = 0xB16 219 val Mhpmcounter23 = 0xB17 220 val Mhpmcounter24 = 0xB18 221 val Mhpmcounter25 = 0xB19 222 val Mhpmcounter26 = 0xB1A 223 val Mhpmcounter27 = 0xB1B 224 val Mhpmcounter28 = 0xB1C 225 val Mhpmcounter29 = 0xB1D 226 val Mhpmcounter30 = 0xB1E 227 val Mhpmcounter31 = 0xB1F 228 229 val Mcountinhibit = 0x320 230 val Mhpmevent3 = 0x323 231 val Mhpmevent4 = 0x324 232 val Mhpmevent5 = 0x325 233 val Mhpmevent6 = 0x326 234 val Mhpmevent7 = 0x327 235 val Mhpmevent8 = 0x328 236 val Mhpmevent9 = 0x329 237 val Mhpmevent10 = 0x32A 238 val Mhpmevent11 = 0x32B 239 val Mhpmevent12 = 0x32C 240 val Mhpmevent13 = 0x32D 241 val Mhpmevent14 = 0x32E 242 val Mhpmevent15 = 0x32F 243 val Mhpmevent16 = 0x330 244 val Mhpmevent17 = 0x331 245 val Mhpmevent18 = 0x332 246 val Mhpmevent19 = 0x333 247 val Mhpmevent20 = 0x334 248 val Mhpmevent21 = 0x335 249 val Mhpmevent22 = 0x336 250 val Mhpmevent23 = 0x337 251 val Mhpmevent24 = 0x338 252 val Mhpmevent25 = 0x339 253 val Mhpmevent26 = 0x33A 254 val Mhpmevent27 = 0x33B 255 val Mhpmevent28 = 0x33C 256 val Mhpmevent29 = 0x33D 257 val Mhpmevent30 = 0x33E 258 val Mhpmevent31 = 0x33F 259 260 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 261 262 // Trigger Registers 263 val Tselect = 0x7A0 264 val Tdata1 = 0x7A1 265 val Tdata2 = 0x7A2 266 val Tinfo = 0x7A4 267 val Tcontrol = 0x7A5 268 269 // Debug Mode Registers 270 val Dcsr = 0x7B0 271 val Dpc = 0x7B1 272 val Dscratch0 = 0x7B2 273 val Dscratch1 = 0x7B3 274 275 def privEcall = 0x000.U 276 def privEbreak = 0x001.U 277 def privMret = 0x302.U 278 def privSret = 0x102.U 279 def privUret = 0x002.U 280 def privDret = 0x7b2.U 281 282 def ModeM = 0x3.U 283 def ModeH = 0x2.U 284 def ModeS = 0x1.U 285 def ModeU = 0x0.U 286 287 def IRQ_USIP = 0 288 def IRQ_SSIP = 1 289 def IRQ_VSSIP = 2 290 def IRQ_MSIP = 3 291 292 def IRQ_UTIP = 4 293 def IRQ_STIP = 5 294 def IRQ_VSTIP = 6 295 def IRQ_MTIP = 7 296 297 def IRQ_UEIP = 8 298 def IRQ_SEIP = 9 299 def IRQ_VSEIP = 10 300 def IRQ_MEIP = 11 301 302 def IRQ_SGEIP = 12 303 def IRQ_DEBUG = 13 304 305 val Hgatp_Mode_len = 4 306 val Hgatp_Vmid_len = 16 307 val Hgatp_Addr_len = 44 308 309 val Satp_Mode_len = 4 310 val Satp_Asid_len = 16 311 val Satp_Addr_len = 44 312 def satp_part_wmask(max_length: Int, length: Int) : UInt = { 313 require(length > 0 && length <= max_length) 314 ((1L << length) - 1).U(max_length.W) 315 } 316 317 val IntPriority = Seq( 318 IRQ_DEBUG, 319 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 320 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 321 IRQ_UEIP, IRQ_USIP, IRQ_UTIP, 322 IRQ_VSEIP, IRQ_VSSIP, IRQ_VSTIP, IRQ_SGEIP 323 ) 324 325 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt, virt: Bool, hasH: Bool): UInt = { 326 val readOnly = addr(11, 10) === "b11".U 327 val lowestAccessPrivilegeLevel = addr(9,8) 328 val priv = Mux(mode === ModeS, ModeH, mode) 329 val ret = Wire(Bool()) //0.U: normal, 1.U: illegal_instruction, 2.U: virtual instruction 330 when (lowestAccessPrivilegeLevel === ModeH && !hasH){ 331 ret := 1.U 332 }.elsewhen (readOnly && wen) { 333 ret := 1.U 334 }.elsewhen (priv < lowestAccessPrivilegeLevel) { 335 when(virt && lowestAccessPrivilegeLevel <= ModeH){ 336 ret := 2.U 337 }.otherwise{ 338 ret := 1.U 339 } 340 }.otherwise{ 341 ret := 0.U 342 } 343 ret 344 } 345 346 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 347 val index = UIntToOH(addr & 31.U) 348 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 349 } 350 351 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 352 // debug mode write only regs 353 val isDebugReg = addr(11, 4) === "h7b".U 354 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 355 } 356 357 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 358 val isTriggerReg = addr(11, 4) === "h7a".U 359 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 360 } 361} 362object CSRConst extends HasCSRConst