1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend.fu.util 17 18import chisel3._ 19import chisel3.util._ 20import utils._ 21import xiangshan._ 22import xiangshan.backend._ 23import utils.XSDebug 24 25trait HasCSRConst { 26 27 // User Trap Setup 28 val Ustatus = 0x000 29 val Uie = 0x004 30 val Utvec = 0x005 31 32 // User Trap Handling 33 val Uscratch = 0x040 34 val Uepc = 0x041 35 val Ucause = 0x042 36 val Utval = 0x043 37 val Uip = 0x044 38 39 // User Floating-Point CSRs (not implemented) 40 val Fflags = 0x001 41 val Frm = 0x002 42 val Fcsr = 0x003 43 44 // User Counter/Timers 45 val Cycle = 0xC00 46 val Time = 0xC01 47 val Instret = 0xC02 48 49 // Supervisor Trap Setup 50 val Sstatus = 0x100 51 val Sedeleg = 0x102 52 val Sideleg = 0x103 53 val Sie = 0x104 54 val Stvec = 0x105 55 val Scounteren = 0x106 56 57 // Supervisor Trap Handling 58 val Sscratch = 0x140 59 val Sepc = 0x141 60 val Scause = 0x142 61 val Stval = 0x143 62 val Sip = 0x144 63 64 // Supervisor Protection and Translation 65 val Satp = 0x180 66 67 // Supervisor Custom Read/Write 68 val Sbpctl = 0x5C0 69 val Spfctl = 0x5C1 70 val Slvpredctl = 0x5C2 71 val Smblockctl = 0x5C3 72 val Srnctl = 0x5C4 73 74 val Sdsid = 0x9C0 75 76 // Machine Information Registers 77 val Mvendorid = 0xF11 78 val Marchid = 0xF12 79 val Mimpid = 0xF13 80 val Mhartid = 0xF14 81 82 // Machine Trap Setup 83 val Mstatus = 0x300 84 val Misa = 0x301 85 val Medeleg = 0x302 86 val Mideleg = 0x303 87 val Mie = 0x304 88 val Mtvec = 0x305 89 val Mcounteren = 0x306 90 91 // Machine Trap Handling 92 val Mscratch = 0x340 93 val Mepc = 0x341 94 val Mcause = 0x342 95 val Mtval = 0x343 96 val Mip = 0x344 97 98 // Machine Memory Protection 99 // TBD 100 val Pmpcfg0 = 0x3A0 101 val Pmpcfg1 = 0x3A1 102 val Pmpcfg2 = 0x3A2 103 val Pmpcfg3 = 0x3A3 104 val PmpaddrBase = 0x3B0 105 106 // Machine Counter/Timers 107 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 108 // 0xB80 - 0x89F are also used as perfcnt csr 109 val Mcycle = 0xb00 110 val Minstret = 0xb02 111 112 val Mhpmcounter3 = 0xB03 113 val Mhpmcounter4 = 0xB04 114 val Mhpmcounter5 = 0xB05 115 val Mhpmcounter6 = 0xB06 116 val Mhpmcounter7 = 0xB07 117 val Mhpmcounter8 = 0xB08 118 val Mhpmcounter9 = 0xB09 119 val Mhpmcounter10 = 0xB0A 120 val Mhpmcounter11 = 0xB0B 121 val Mhpmcounter12 = 0xB0C 122 val Mhpmcounter13 = 0xB0D 123 val Mhpmcounter14 = 0xB0E 124 val Mhpmcounter15 = 0xB0F 125 val Mhpmcounter16 = 0xB10 126 val Mhpmcounter17 = 0xB11 127 val Mhpmcounter18 = 0xB12 128 val Mhpmcounter19 = 0xB13 129 val Mhpmcounter20 = 0xB14 130 val Mhpmcounter21 = 0xB15 131 val Mhpmcounter22 = 0xB16 132 val Mhpmcounter23 = 0xB17 133 val Mhpmcounter24 = 0xB18 134 val Mhpmcounter25 = 0xB19 135 val Mhpmcounter26 = 0xB1A 136 val Mhpmcounter27 = 0xB1B 137 val Mhpmcounter28 = 0xB1C 138 val Mhpmcounter29 = 0xB1D 139 val Mhpmcounter30 = 0xB1E 140 val Mhpmcounter31 = 0xB1F 141 142 // Machine Counter Setup (not implemented) 143 val Mcountinhibit = 0x320 144 val Mhpmevent3 = 0x323 145 val Mhpmevent4 = 0x324 146 val Mhpmevent5 = 0x325 147 val Mhpmevent6 = 0x326 148 val Mhpmevent7 = 0x327 149 val Mhpmevent8 = 0x328 150 val Mhpmevent9 = 0x329 151 val Mhpmevent10 = 0x32A 152 val Mhpmevent11 = 0x32B 153 val Mhpmevent12 = 0x32C 154 val Mhpmevent13 = 0x32D 155 val Mhpmevent14 = 0x32E 156 val Mhpmevent15 = 0x32F 157 val Mhpmevent16 = 0x330 158 val Mhpmevent17 = 0x331 159 val Mhpmevent18 = 0x332 160 val Mhpmevent19 = 0x333 161 val Mhpmevent20 = 0x334 162 val Mhpmevent21 = 0x335 163 val Mhpmevent22 = 0x336 164 val Mhpmevent23 = 0x337 165 val Mhpmevent24 = 0x338 166 val Mhpmevent25 = 0x339 167 val Mhpmevent26 = 0x33A 168 val Mhpmevent27 = 0x33B 169 val Mhpmevent28 = 0x33C 170 val Mhpmevent29 = 0x33D 171 val Mhpmevent30 = 0x33E 172 val Mhpmevent31 = 0x33F 173 174 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 175 // Debug Mode Registers (not implemented) 176 177 def privEcall = 0x000.U 178 def privEbreak = 0x001.U 179 def privMret = 0x302.U 180 def privSret = 0x102.U 181 def privUret = 0x002.U 182 183 def ModeM = 0x3.U 184 def ModeH = 0x2.U 185 def ModeS = 0x1.U 186 def ModeU = 0x0.U 187 188 def IRQ_UEIP = 0 189 def IRQ_SEIP = 1 190 def IRQ_MEIP = 3 191 192 def IRQ_UTIP = 4 193 def IRQ_STIP = 5 194 def IRQ_MTIP = 7 195 196 def IRQ_USIP = 8 197 def IRQ_SSIP = 9 198 def IRQ_MSIP = 11 199 200 val IntPriority = Seq( 201 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 202 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 203 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 204 ) 205 206 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 207 val readOnly = addr(11,10) === "b11".U 208 val lowestAccessPrivilegeLevel = addr(9,8) 209 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 210 } 211 212 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 213 val index = UIntToOH(addr & 31.U) 214 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 215 } 216} 217