1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.rocket.CSRs 22 23trait HasCSRConst { 24 // Supervisor Custom Read/Write 25 val Sbpctl = 0x5C0 26 val Spfctl = 0x5C1 27 val Slvpredctl = 0x5C2 28 val Smblockctl = 0x5C3 29 val Srnctl = 0x5C4 30 /** 0x5C5-0x5E5 for cache instruction register*/ 31 val Scachebase = 0x5C5 32 33 // Machine level PMA TODO: remove this 34 val PmacfgBase = 0x7C0 35 val PmaaddrBase = 0x7C8 // 64 entry at most 36 37 def privEcall = 0x000.U 38 def privEbreak = 0x001.U 39 def privMNret = 0x702.U 40 def privMret = 0x302.U 41 def privSret = 0x102.U 42 def privUret = 0x002.U 43 def privDret = 0x7b2.U 44 45 def ModeM = 0x3.U 46 def ModeH = 0x2.U 47 def ModeS = 0x1.U 48 def ModeU = 0x0.U 49 50 def IRQ_USIP = 0 51 def IRQ_SSIP = 1 52 def IRQ_VSSIP = 2 53 def IRQ_MSIP = 3 54 55 def IRQ_UTIP = 4 56 def IRQ_STIP = 5 57 def IRQ_VSTIP = 6 58 def IRQ_MTIP = 7 59 60 def IRQ_UEIP = 8 61 def IRQ_SEIP = 9 62 def IRQ_VSEIP = 10 63 def IRQ_MEIP = 11 64 65 def IRQ_SGEIP = 12 66 def IRQ_DEBUG = 17 67 68 val Hgatp_Mode_len = 4 69 val Hgatp_Vmid_len = 16 70 val Hgatp_Addr_len = 44 71 72 val Satp_Mode_len = 4 73 val Satp_Asid_len = 16 74 val Satp_Addr_len = 44 75 def satp_part_wmask(max_length: Int, length: Int) : UInt = { 76 require(length > 0 && length <= max_length) 77 ((1L << length) - 1).U(max_length.W) 78 } 79 80 val IntPriority = Seq( 81 IRQ_DEBUG, 82 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 83 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 84 IRQ_UEIP, IRQ_USIP, IRQ_UTIP, 85 IRQ_VSEIP, IRQ_VSSIP, IRQ_VSTIP, IRQ_SGEIP 86 ) 87 88 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt, virt: Bool, hasH: Bool): UInt = { 89 val readOnly = addr(11, 10) === "b11".U 90 val lowestAccessPrivilegeLevel = addr(9,8) 91 val priv = Mux(mode === ModeS, ModeH, mode) 92 val ret = Wire(Bool()) //0.U: normal, 1.U: illegal_instruction, 2.U: virtual instruction 93 when (lowestAccessPrivilegeLevel === ModeH && !hasH){ 94 ret := 1.U 95 }.elsewhen (readOnly && wen) { 96 ret := 1.U 97 }.elsewhen (priv < lowestAccessPrivilegeLevel) { 98 when(virt && lowestAccessPrivilegeLevel <= ModeH){ 99 ret := 2.U 100 }.otherwise{ 101 ret := 1.U 102 } 103 }.otherwise{ 104 ret := 0.U 105 } 106 ret 107 } 108 109 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 110 val index = UIntToOH(addr & 31.U) 111 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 112 } 113 114 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 115 // debug mode write only regs 116 val isDebugReg = addr(11, 4) === "h7b".U 117 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 118 } 119 120 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 121 val isTriggerReg = addr(11, 4) === "h7a".U 122 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 123 } 124} 125object CSRConst extends HasCSRConst 126