1package xiangshan.backend.fu.util 2 3import chisel3._ 4import chisel3.ExcitingUtils.{ConnectionType, Debug} 5import chisel3.util._ 6import utils._ 7import xiangshan._ 8import xiangshan.backend._ 9import utils.XSDebug 10 11trait HasCSRConst { 12 13 // User Trap Setup 14 val Ustatus = 0x000 15 val Uie = 0x004 16 val Utvec = 0x005 17 18 // User Trap Handling 19 val Uscratch = 0x040 20 val Uepc = 0x041 21 val Ucause = 0x042 22 val Utval = 0x043 23 val Uip = 0x044 24 25 // User Floating-Point CSRs (not implemented) 26 val Fflags = 0x001 27 val Frm = 0x002 28 val Fcsr = 0x003 29 30 // User Counter/Timers 31 val Cycle = 0xC00 32 val Time = 0xC01 33 val Instret = 0xC02 34 35 // Supervisor Trap Setup 36 val Sstatus = 0x100 37 val Sedeleg = 0x102 38 val Sideleg = 0x103 39 val Sie = 0x104 40 val Stvec = 0x105 41 val Scounteren = 0x106 42 43 // Supervisor Trap Handling 44 val Sscratch = 0x140 45 val Sepc = 0x141 46 val Scause = 0x142 47 val Stval = 0x143 48 val Sip = 0x144 49 50 // Supervisor Protection and Translation 51 val Satp = 0x180 52 53 // Machine Information Registers 54 val Mvendorid = 0xF11 55 val Marchid = 0xF12 56 val Mimpid = 0xF13 57 val Mhartid = 0xF14 58 59 // Machine Trap Setup 60 val Mstatus = 0x300 61 val Misa = 0x301 62 val Medeleg = 0x302 63 val Mideleg = 0x303 64 val Mie = 0x304 65 val Mtvec = 0x305 66 val Mcounteren = 0x306 67 68 // Machine Trap Handling 69 val Mscratch = 0x340 70 val Mepc = 0x341 71 val Mcause = 0x342 72 val Mtval = 0x343 73 val Mip = 0x344 74 75 // Machine Memory Protection 76 // TBD 77 val Pmpcfg0 = 0x3A0 78 val Pmpcfg1 = 0x3A1 79 val Pmpcfg2 = 0x3A2 80 val Pmpcfg3 = 0x3A3 81 val PmpaddrBase = 0x3B0 82 83 // Machine Counter/Timers 84 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 85 // 0xB80 - 0x89F are also used as perfcnt csr 86 val Mcycle = 0xb00 87 val Minstret = 0xb02 88 89 val Mhpmcounter3 = 0xB03 90 val Mhpmcounter4 = 0xB04 91 val Mhpmcounter5 = 0xB05 92 val Mhpmcounter6 = 0xB06 93 val Mhpmcounter7 = 0xB07 94 val Mhpmcounter8 = 0xB08 95 val Mhpmcounter9 = 0xB09 96 val Mhpmcounter10 = 0xB0A 97 val Mhpmcounter11 = 0xB0B 98 val Mhpmcounter12 = 0xB0C 99 val Mhpmcounter13 = 0xB0D 100 val Mhpmcounter14 = 0xB0E 101 val Mhpmcounter15 = 0xB0F 102 val Mhpmcounter16 = 0xB10 103 val Mhpmcounter17 = 0xB11 104 val Mhpmcounter18 = 0xB12 105 val Mhpmcounter19 = 0xB13 106 val Mhpmcounter20 = 0xB14 107 val Mhpmcounter21 = 0xB15 108 val Mhpmcounter22 = 0xB16 109 val Mhpmcounter23 = 0xB17 110 val Mhpmcounter24 = 0xB18 111 val Mhpmcounter25 = 0xB19 112 val Mhpmcounter26 = 0xB1A 113 val Mhpmcounter27 = 0xB1B 114 val Mhpmcounter28 = 0xB1C 115 val Mhpmcounter29 = 0xB1D 116 val Mhpmcounter30 = 0xB1E 117 val Mhpmcounter31 = 0xB1F 118 119 // Machine Counter Setup (not implemented) 120 val Mcountinhibit = 0x320 121 val Mhpmevent3 = 0x323 122 val Mhpmevent4 = 0x324 123 val Mhpmevent5 = 0x325 124 val Mhpmevent6 = 0x326 125 val Mhpmevent7 = 0x327 126 val Mhpmevent8 = 0x328 127 val Mhpmevent9 = 0x329 128 val Mhpmevent10 = 0x32A 129 val Mhpmevent11 = 0x32B 130 val Mhpmevent12 = 0x32C 131 val Mhpmevent13 = 0x32D 132 val Mhpmevent14 = 0x32E 133 val Mhpmevent15 = 0x32F 134 val Mhpmevent16 = 0x330 135 val Mhpmevent17 = 0x331 136 val Mhpmevent18 = 0x332 137 val Mhpmevent19 = 0x333 138 val Mhpmevent20 = 0x334 139 val Mhpmevent21 = 0x335 140 val Mhpmevent22 = 0x336 141 val Mhpmevent23 = 0x337 142 val Mhpmevent24 = 0x338 143 val Mhpmevent25 = 0x339 144 val Mhpmevent26 = 0x33A 145 val Mhpmevent27 = 0x33B 146 val Mhpmevent28 = 0x33C 147 val Mhpmevent29 = 0x33D 148 val Mhpmevent30 = 0x33E 149 val Mhpmevent31 = 0x33F 150 151 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 152 // Debug Mode Registers (not implemented) 153 154 def privEcall = 0x000.U 155 def privEbreak = 0x001.U 156 def privMret = 0x302.U 157 def privSret = 0x102.U 158 def privUret = 0x002.U 159 160 def ModeM = 0x3.U 161 def ModeH = 0x2.U 162 def ModeS = 0x1.U 163 def ModeU = 0x0.U 164 165 def IRQ_UEIP = 0 166 def IRQ_SEIP = 1 167 def IRQ_MEIP = 3 168 169 def IRQ_UTIP = 4 170 def IRQ_STIP = 5 171 def IRQ_MTIP = 7 172 173 def IRQ_USIP = 8 174 def IRQ_SSIP = 9 175 def IRQ_MSIP = 11 176 177 val IntPriority = Seq( 178 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 179 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 180 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 181 ) 182 183 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 184 val readOnly = addr(11,10) === "b11".U 185 val lowestAccessPrivilegeLevel = addr(9,8) 186 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 187 } 188}