1package xiangshan.backend.fu 2 3import chisel3._ 4import chisel3.util._ 5import utils.SignExt 6import xiangshan.backend.fu.fpu.util.CSA3_2 7 8/** A Radix-4 SRT Integer Divider 9 * 10 * 2 ~ (5 + (len+3)/2) cycles are needed for each division. 11 */ 12class SRT4Divider(len: Int) extends AbstractDivider(len) { 13 14 val s_idle :: s_lzd :: s_normlize :: s_recurrence :: s_recovery :: s_finish :: Nil = Enum(6) 15 val state = RegInit(s_idle) 16 val newReq = (state === s_idle) && io.in.fire() 17 val cnt_next = Wire(UInt(log2Up((len+3)/2).W)) 18 val cnt = RegEnable(cnt_next, state===s_normlize || state===s_recurrence) 19 val rec_enough = cnt_next === 0.U 20 21 def abs(a: UInt, sign: Bool): (Bool, UInt) = { 22 val s = a(len - 1) && sign 23 (s, Mux(s, -a, a)) 24 } 25 val (a, b) = (io.in.bits.src(0), io.in.bits.src(1)) 26 val uop = io.in.bits.uop 27 val (aSign, aVal) = abs(a, sign) 28 val (bSign, bVal) = abs(b, sign) 29 val aSignReg = RegEnable(aSign, newReq) 30 val qSignReg = RegEnable(aSign ^ bSign, newReq) 31 val uopReg = RegEnable(uop, newReq) 32 val ctrlReg = RegEnable(ctrl, newReq) 33 val divZero = b === 0.U 34 val divZeroReg = RegEnable(divZero, newReq) 35 36 val kill = state=/=s_idle && uopReg.roqIdx.needFlush(io.redirectIn) 37 38 switch(state){ 39 is(s_idle){ 40 when(io.in.fire()){ state := Mux(divZero, s_finish, s_lzd) } 41 } 42 is(s_lzd){ // leading zero detection 43 state := s_normlize 44 } 45 is(s_normlize){ // shift a/b 46 state := s_recurrence 47 } 48 is(s_recurrence){ // (ws[j+1], wc[j+1]) = 4(ws[j],wc[j]) - q(j+1)*d 49 when(rec_enough){ state := s_recovery } 50 } 51 is(s_recovery){ // if rem < 0, rem = rem + d 52 state := s_finish 53 } 54 is(s_finish){ 55 when(io.out.fire()){ state := s_idle } 56 } 57 } 58 when(kill){ 59 state := s_idle 60 } 61 62 /** Calculate abs(a)/abs(b) by recurrence 63 * 64 * ws, wc: partial remainder in carry-save form, 65 * in recurrence steps, ws/wc = 4ws[j]/4wc[j]; 66 * in recovery step, ws/wc = ws[j]/wc[j]; 67 * in final step, ws = abs(a)/abs(b). 68 * 69 * d: normlized divisor(1/2<=d<1) 70 * 71 * wLen = 3 integer bits + (len+1) frac bits 72 */ 73 def wLen = 3 + len + 1 74 val ws, wc = Reg(UInt(wLen.W)) 75 val ws_next, wc_next = Wire(UInt(wLen.W)) 76 val d = Reg(UInt(wLen.W)) 77 78 val aLeadingZeros = RegEnable( 79 next = PriorityEncoder(ws(len-1, 0).asBools().reverse), 80 enable = state===s_lzd 81 ) 82 val bLeadingZeros = RegEnable( 83 next = PriorityEncoder(d(len-1, 0).asBools().reverse), 84 enable = state===s_lzd 85 ) 86 val diff = Cat(0.U(1.W), bLeadingZeros).asSInt() - Cat(0.U(1.W), aLeadingZeros).asSInt() 87 val isNegDiff = diff(diff.getWidth - 1) 88 val quotientBits = Mux(isNegDiff, 0.U, diff.asUInt()) 89 val qBitsIsOdd = quotientBits(0) 90 val recoveryShift = RegEnable(len.U - bLeadingZeros, state===s_normlize) 91 val a_shifted, b_shifted = Wire(UInt(len.W)) 92 a_shifted := Mux(isNegDiff, 93 ws(len-1, 0) << bLeadingZeros, 94 ws(len-1, 0) << aLeadingZeros 95 ) 96 b_shifted := d(len-1, 0) << bLeadingZeros 97 98 val rem_temp = ws + wc 99 val rem_fixed = Mux(rem_temp(wLen-1), rem_temp + d, rem_temp) 100 val rem_abs = (rem_fixed << recoveryShift)(2*len, len+1) 101 102 when(newReq){ 103 ws := Cat(0.U(4.W), Mux(divZero, a, aVal)) 104 wc := 0.U 105 d := Cat(0.U(4.W), bVal) 106 }.elsewhen(state === s_normlize){ 107 d := Cat(0.U(3.W), b_shifted, 0.U(1.W)) 108 ws := Mux(qBitsIsOdd, a_shifted, a_shifted << 1) 109 }.elsewhen(state === s_recurrence){ 110 ws := Mux(rec_enough, ws_next, ws_next << 2) 111 wc := Mux(rec_enough, wc_next, wc_next << 2) 112 }.elsewhen(state === s_recovery){ 113 ws := rem_abs 114 } 115 116 cnt_next := Mux(state === s_normlize, (quotientBits + 3.U) >> 1, cnt - 1.U) 117 118 /** Quotient selection 119 * 120 * the quotient selection table use truncated 7-bit remainder 121 * and 3-bit divisor 122 */ 123 val sel_0 :: sel_d :: sel_dx2 :: sel_neg_d :: sel_neg_dx2 :: Nil = Enum(5) 124 val dx2, neg_d, neg_dx2 = Wire(UInt(wLen.W)) 125 dx2 := d << 1 126 neg_d := (~d).asUInt() // add '1' in carry-save adder later 127 neg_dx2 := neg_d << 1 128 129 val q_sel = Wire(UInt(3.W)) 130 val wc_adj = MuxLookup(q_sel, 0.U(2.W), Seq( 131 sel_d -> 1.U(2.W), 132 sel_dx2 -> 2.U(2.W) 133 )) 134 135 val w_truncated = (ws(wLen-1, wLen-1-6) + wc(wLen-1, wLen-1-6)).asSInt() 136 val d_truncated = d(len-1, len-3) 137 138 val qSelTable = Array( 139 Array(12, 4, -4, -13), 140 Array(14, 4, -6, -15), 141 Array(15, 4, -6, -16), 142 Array(16, 4, -6, -18), 143 Array(18, 6, -8, -20), 144 Array(20, 6, -8, -20), 145 Array(20, 8, -8, -22), 146 Array(24, 8, -8, -24) 147 ) 148 149 // ge(x): w_truncated >= x 150 var ge = Map[Int, Bool]() 151 for(row <- qSelTable){ 152 for(k <- row){ 153 if(!ge.contains(k)) ge = ge + (k -> (w_truncated >= k.S(7.W))) 154 } 155 } 156 q_sel := MuxLookup(d_truncated, sel_0, 157 qSelTable.map(x => 158 MuxCase(sel_neg_dx2, Seq( 159 ge(x(0)) -> sel_dx2, 160 ge(x(1)) -> sel_d, 161 ge(x(2)) -> sel_0, 162 ge(x(3)) -> sel_neg_d 163 )) 164 ).zipWithIndex.map({case(v, i) => i.U -> v}) 165 ) 166 167 /** Calculate (ws[j+1],wc[j+1]) by a [3-2]carry-save adder 168 * 169 * (ws[j+1], wc[j+1]) = 4(ws[j],wc[j]) - q(j+1)*d 170 */ 171 val csa = Module(new CSA3_2(wLen)) 172 csa.io.in(0) := ws 173 csa.io.in(1) := Cat(wc(wLen-1, 2), wc_adj) 174 csa.io.in(2) := MuxLookup(q_sel, 0.U, Seq( 175 sel_d -> neg_d, 176 sel_dx2 -> neg_dx2, 177 sel_neg_d -> d, 178 sel_neg_dx2 -> dx2 179 )) 180 ws_next := csa.io.out(0) 181 wc_next := csa.io.out(1) << 1 182 183 // On the fly quotient conversion 184 val q, qm = Reg(UInt(len.W)) 185 when(newReq){ 186 q := 0.U 187 qm := 0.U 188 }.elsewhen(state === s_recurrence){ 189 val qMap = Seq( 190 sel_0 -> (q, 0), 191 sel_d -> (q, 1), 192 sel_dx2 -> (q, 2), 193 sel_neg_d -> (qm, 3), 194 sel_neg_dx2 -> (qm, 2) 195 ) 196 q := MuxLookup(q_sel, 0.U, 197 qMap.map(m => m._1 -> Cat(m._2._1(len-3, 0), m._2._2.U(2.W))) 198 ) 199 val qmMap = Seq( 200 sel_0 -> (qm, 3), 201 sel_d -> (q, 0), 202 sel_dx2 -> (q, 1), 203 sel_neg_d -> (qm, 2), 204 sel_neg_dx2 -> (qm, 1) 205 ) 206 qm := MuxLookup(q_sel, 0.U, 207 qmMap.map(m => m._1 -> Cat(m._2._1(len-3, 0), m._2._2.U(2.W))) 208 ) 209 }.elsewhen(state === s_recovery){ 210 q := Mux(rem_temp(wLen-1), qm, q) 211 } 212 213 214 val remainder = Mux(aSignReg, -ws(len-1, 0), ws(len-1, 0)) 215 val quotient = Mux(qSignReg, -q, q) 216 217 val res = Mux(ctrlReg.isHi, 218 Mux(divZeroReg, ws(len-1, 0), remainder), 219 Mux(divZeroReg, Fill(len, 1.U(1.W)), quotient) 220 ) 221 222 io.in.ready := state===s_idle 223 io.out.valid := state===s_finish && !kill 224 io.out.bits.data := Mux(ctrlReg.isW, 225 SignExt(res(31, 0), len), 226 res 227 ) 228 io.out.bits.uop := uopReg 229 230} 231