1package xiangshan.backend.fu 2 3import chisel3._ 4import chisel3.util._ 5import utils.SignExt 6import xiangshan.backend.fu.util.CSA3_2 7 8/** A Radix-4 SRT Integer Divider 9 * 10 * 2 ~ (5 + (len+3)/2) cycles are needed for each division. 11 */ 12class SRT4Divider(len: Int) extends AbstractDivider(len) { 13 14 val s_idle :: s_lzd :: s_normlize :: s_recurrence :: s_recovery :: s_finish :: Nil = Enum(6) 15 val state = RegInit(s_idle) 16 val newReq = (state === s_idle) && io.in.fire() 17 val cnt_next = Wire(UInt(log2Up((len+3)/2).W)) 18 val cnt = RegEnable(cnt_next, state===s_normlize || state===s_recurrence) 19 val rec_enough = cnt_next === 0.U 20 21 def abs(a: UInt, sign: Bool): (Bool, UInt) = { 22 val s = a(len - 1) && sign 23 (s, Mux(s, -a, a)) 24 } 25 val (a, b) = (io.in.bits.src(0), io.in.bits.src(1)) 26 val uop = io.in.bits.uop 27 val (aSign, aVal) = abs(a, sign) 28 val (bSign, bVal) = abs(b, sign) 29 val aSignReg = RegEnable(aSign, newReq) 30 val qSignReg = RegEnable(aSign ^ bSign, newReq) 31 val uopReg = RegEnable(uop, newReq) 32 val ctrlReg = RegEnable(ctrl, newReq) 33 val divZero = b === 0.U 34 val divZeroReg = RegEnable(divZero, newReq) 35 36 val kill = state=/=s_idle && uopReg.roqIdx.needFlush(io.redirectIn) 37 38 switch(state){ 39 is(s_idle){ 40 when (io.in.fire() && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn)) { 41 state := Mux(divZero, s_finish, s_lzd) 42 } 43 } 44 is(s_lzd){ // leading zero detection 45 state := s_normlize 46 } 47 is(s_normlize){ // shift a/b 48 state := s_recurrence 49 } 50 is(s_recurrence){ // (ws[j+1], wc[j+1]) = 4(ws[j],wc[j]) - q(j+1)*d 51 when(rec_enough){ state := s_recovery } 52 } 53 is(s_recovery){ // if rem < 0, rem = rem + d 54 state := s_finish 55 } 56 is(s_finish){ 57 when(io.out.fire()){ state := s_idle } 58 } 59 } 60 when(kill){ 61 state := s_idle 62 } 63 64 /** Calculate abs(a)/abs(b) by recurrence 65 * 66 * ws, wc: partial remainder in carry-save form, 67 * in recurrence steps, ws/wc = 4ws[j]/4wc[j]; 68 * in recovery step, ws/wc = ws[j]/wc[j]; 69 * in final step, ws = abs(a)/abs(b). 70 * 71 * d: normlized divisor(1/2<=d<1) 72 * 73 * wLen = 3 integer bits + (len+1) frac bits 74 */ 75 def wLen = 3 + len + 1 76 val ws, wc = Reg(UInt(wLen.W)) 77 val ws_next, wc_next = Wire(UInt(wLen.W)) 78 val d = Reg(UInt(wLen.W)) 79 80 val aLeadingZeros = RegEnable( 81 next = PriorityEncoder(ws(len-1, 0).asBools().reverse), 82 enable = state===s_lzd 83 ) 84 val bLeadingZeros = RegEnable( 85 next = PriorityEncoder(d(len-1, 0).asBools().reverse), 86 enable = state===s_lzd 87 ) 88 val diff = Cat(0.U(1.W), bLeadingZeros).asSInt() - Cat(0.U(1.W), aLeadingZeros).asSInt() 89 val isNegDiff = diff(diff.getWidth - 1) 90 val quotientBits = Mux(isNegDiff, 0.U, diff.asUInt()) 91 val qBitsIsOdd = quotientBits(0) 92 val recoveryShift = RegEnable(len.U - bLeadingZeros, state===s_normlize) 93 val a_shifted, b_shifted = Wire(UInt(len.W)) 94 a_shifted := Mux(isNegDiff, 95 ws(len-1, 0) << bLeadingZeros, 96 ws(len-1, 0) << aLeadingZeros 97 ) 98 b_shifted := d(len-1, 0) << bLeadingZeros 99 100 val rem_temp = ws + wc 101 val rem_fixed = Mux(rem_temp(wLen-1), rem_temp + d, rem_temp) 102 val rem_abs = (rem_fixed << recoveryShift)(2*len, len+1) 103 104 when(newReq){ 105 ws := Cat(0.U(4.W), Mux(divZero, a, aVal)) 106 wc := 0.U 107 d := Cat(0.U(4.W), bVal) 108 }.elsewhen(state === s_normlize){ 109 d := Cat(0.U(3.W), b_shifted, 0.U(1.W)) 110 ws := Mux(qBitsIsOdd, a_shifted, a_shifted << 1) 111 }.elsewhen(state === s_recurrence){ 112 ws := Mux(rec_enough, ws_next, ws_next << 2) 113 wc := Mux(rec_enough, wc_next, wc_next << 2) 114 }.elsewhen(state === s_recovery){ 115 ws := rem_abs 116 } 117 118 cnt_next := Mux(state === s_normlize, (quotientBits + 3.U) >> 1, cnt - 1.U) 119 120 /** Quotient selection 121 * 122 * the quotient selection table use truncated 7-bit remainder 123 * and 3-bit divisor 124 */ 125 val sel_0 :: sel_d :: sel_dx2 :: sel_neg_d :: sel_neg_dx2 :: Nil = Enum(5) 126 val dx2, neg_d, neg_dx2 = Wire(UInt(wLen.W)) 127 dx2 := d << 1 128 neg_d := (~d).asUInt() // add '1' in carry-save adder later 129 neg_dx2 := neg_d << 1 130 131 val q_sel = Wire(UInt(3.W)) 132 val wc_adj = MuxLookup(q_sel, 0.U(2.W), Seq( 133 sel_d -> 1.U(2.W), 134 sel_dx2 -> 2.U(2.W) 135 )) 136 137 val w_truncated = (ws(wLen-1, wLen-1-6) + wc(wLen-1, wLen-1-6)).asSInt() 138 val d_truncated = d(len-1, len-3) 139 140 val qSelTable = Array( 141 Array(12, 4, -4, -13), 142 Array(14, 4, -6, -15), 143 Array(15, 4, -6, -16), 144 Array(16, 4, -6, -18), 145 Array(18, 6, -8, -20), 146 Array(20, 6, -8, -20), 147 Array(20, 8, -8, -22), 148 Array(24, 8, -8, -24) 149 ) 150 151 // ge(x): w_truncated >= x 152 var ge = Map[Int, Bool]() 153 for(row <- qSelTable){ 154 for(k <- row){ 155 if(!ge.contains(k)) ge = ge + (k -> (w_truncated >= k.S(7.W))) 156 } 157 } 158 q_sel := MuxLookup(d_truncated, sel_0, 159 qSelTable.map(x => 160 MuxCase(sel_neg_dx2, Seq( 161 ge(x(0)) -> sel_dx2, 162 ge(x(1)) -> sel_d, 163 ge(x(2)) -> sel_0, 164 ge(x(3)) -> sel_neg_d 165 )) 166 ).zipWithIndex.map({case(v, i) => i.U -> v}) 167 ) 168 169 /** Calculate (ws[j+1],wc[j+1]) by a [3-2]carry-save adder 170 * 171 * (ws[j+1], wc[j+1]) = 4(ws[j],wc[j]) - q(j+1)*d 172 */ 173 val csa = Module(new CSA3_2(wLen)) 174 csa.io.in(0) := ws 175 csa.io.in(1) := Cat(wc(wLen-1, 2), wc_adj) 176 csa.io.in(2) := MuxLookup(q_sel, 0.U, Seq( 177 sel_d -> neg_d, 178 sel_dx2 -> neg_dx2, 179 sel_neg_d -> d, 180 sel_neg_dx2 -> dx2 181 )) 182 ws_next := csa.io.out(0) 183 wc_next := csa.io.out(1) << 1 184 185 // On the fly quotient conversion 186 val q, qm = Reg(UInt(len.W)) 187 when(newReq){ 188 q := 0.U 189 qm := 0.U 190 }.elsewhen(state === s_recurrence){ 191 val qMap = Seq( 192 sel_0 -> (q, 0), 193 sel_d -> (q, 1), 194 sel_dx2 -> (q, 2), 195 sel_neg_d -> (qm, 3), 196 sel_neg_dx2 -> (qm, 2) 197 ) 198 q := MuxLookup(q_sel, 0.U, 199 qMap.map(m => m._1 -> Cat(m._2._1(len-3, 0), m._2._2.U(2.W))) 200 ) 201 val qmMap = Seq( 202 sel_0 -> (qm, 3), 203 sel_d -> (q, 0), 204 sel_dx2 -> (q, 1), 205 sel_neg_d -> (qm, 2), 206 sel_neg_dx2 -> (qm, 1) 207 ) 208 qm := MuxLookup(q_sel, 0.U, 209 qmMap.map(m => m._1 -> Cat(m._2._1(len-3, 0), m._2._2.U(2.W))) 210 ) 211 }.elsewhen(state === s_recovery){ 212 q := Mux(rem_temp(wLen-1), qm, q) 213 } 214 215 216 val remainder = Mux(aSignReg, -ws(len-1, 0), ws(len-1, 0)) 217 val quotient = Mux(qSignReg, -q, q) 218 219 val res = Mux(ctrlReg.isHi, 220 Mux(divZeroReg, ws(len-1, 0), remainder), 221 Mux(divZeroReg, Fill(len, 1.U(1.W)), quotient) 222 ) 223 224 io.in.ready := state===s_idle 225 io.out.valid := state===s_finish 226 io.out.bits.data := Mux(ctrlReg.isW, 227 SignExt(res(31, 0), len), 228 res 229 ) 230 io.out.bits.uop := uopReg 231 232} 233