1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.ExceptionNO 6import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState, XtvecBundle} 7import xiangshan.backend.fu.NewCSR.CSRDefines.XtvecMode 8import xiangshan.backend.fu.NewCSR.CSRBundleImplicitCast._ 9 10 11class TrapHandleModule extends Module { 12 val io = IO(new TrapHandleIO) 13 14 private val trapInfo = io.in.trapInfo 15 private val privState = io.in.privState 16 private val mideleg = io.in.mideleg.asUInt 17 private val hideleg = io.in.hideleg.asUInt 18 private val medeleg = io.in.medeleg.asUInt 19 private val hedeleg = io.in.hedeleg.asUInt 20 private val mvien = io.in.mvien.asUInt 21 private val hvien = io.in.hvien.asUInt 22 23 private val hasTrap = trapInfo.valid 24 private val hasNMI = hasTrap && trapInfo.bits.nmi 25 private val hasIR = hasTrap && trapInfo.bits.isInterrupt 26 private val hasEX = hasTrap && !trapInfo.bits.isInterrupt 27 28 private val exceptionVec = io.in.trapInfo.bits.trapVec 29 private val intrVec = io.in.trapInfo.bits.intrVec 30 private val hasEXVec = Mux(hasEX, exceptionVec, 0.U) 31 private val hasIRVec = Mux(hasIR, intrVec, 0.U) 32 33 private val interruptGroups: Seq[(Seq[Int], String)] = Seq( 34 InterruptNO.customHighestGroup -> "customHighest", 35 InterruptNO.localHighGroup -> "localHigh", 36 InterruptNO.customMiddleHighGroup -> "customMiddleHigh", 37 InterruptNO.interruptDefaultPrio -> "privArch", 38 InterruptNO.customMiddleLowGroup -> "customMiddleLow", 39 InterruptNO.localLowGroup -> "localLow", 40 InterruptNO.customLowestGroup -> "customLowest", 41 ) 42 43 private val filteredIRQs: Seq[UInt] = interruptGroups.map { 44 case (irqGroup, name) => (getMaskFromIRQGroup(irqGroup) & hasIRVec).suggestName(s"filteredIRQs_$name") 45 } 46 private val hasIRQinGroup: Seq[Bool] = interruptGroups.map { 47 case (irqGroup, name) => dontTouch(Cat(filterIRQs(irqGroup, hasIRVec)).orR.suggestName(s"hasIRQinGroup_$name")) 48 } 49 50 private val highestIRQinGroup: Seq[Vec[Bool]] = interruptGroups zip filteredIRQs map { 51 case ((irqGroup: Seq[Int], name), filteredIRQ: UInt) => 52 produceHighIRInGroup(irqGroup, filteredIRQ).suggestName(s"highestIRQinGroup_$name") 53 } 54 55 private val highestPrioIRVec: Vec[Bool] = MuxCase( 56 0.U.asTypeOf(Vec(64, Bool())), 57 hasIRQinGroup zip highestIRQinGroup map{ case (hasIRQ: Bool, highestIRQ: Vec[Bool]) => hasIRQ -> highestIRQ } 58 ) 59 private val highestPrioNMIVec = Wire(Vec(64, Bool())) 60 highestPrioNMIVec.zipWithIndex.foreach { case (irq, i) => 61 if (NonMaskableIRNO.interruptDefaultPrio.contains(i)) { 62 val higherIRSeq = NonMaskableIRNO.getIRQHigherThan(i) 63 irq := ( 64 higherIRSeq.nonEmpty.B && Cat(higherIRSeq.map(num => !hasIRVec(num))).andR || 65 higherIRSeq.isEmpty.B 66 ) && hasIRVec(i) 67 dontTouch(irq) 68 } else 69 irq := false.B 70 } 71 72 private val highestPrioEXVec = Wire(Vec(64, Bool())) 73 highestPrioEXVec.zipWithIndex.foreach { case (excp, i) => 74 if (ExceptionNO.priorities.contains(i)) { 75 val higherEXSeq = ExceptionNO.getHigherExcpThan(i) 76 excp := ( 77 higherEXSeq.nonEmpty.B && Cat(higherEXSeq.map(num => !hasEXVec(num))).andR || 78 higherEXSeq.isEmpty.B 79 ) && hasEXVec(i) 80 } else 81 excp := false.B 82 } 83 84 private val highestPrioIR = highestPrioIRVec.asUInt 85 private val highestPrioNMI = highestPrioNMIVec.asUInt 86 private val highestPrioEX = highestPrioEXVec.asUInt 87 88 89 private val mIRVec = dontTouch(WireInit(highestPrioIR)) 90 private val hsIRVec = (mIRVec & mideleg) | (mIRVec & mvien & ~mideleg) 91 private val vsIRVec = (hsIRVec & hideleg) | (hsIRVec & hvien & ~hideleg) 92 93 private val mEXVec = highestPrioEX 94 private val hsEXVec = highestPrioEX & medeleg 95 private val vsEXVec = highestPrioEX & medeleg & hedeleg 96 97 // nmi handle in MMode only and default handler is mtvec 98 private val mHasIR = mIRVec.orR 99 private val hsHasIR = hsIRVec.orR & !hasNMI 100 private val vsHasIR = vsIRVec.orR & !hasNMI 101 102 private val mHasEX = mEXVec.orR 103 private val hsHasEX = hsEXVec.orR 104 private val vsHasEX = vsEXVec.orR 105 106 private val mHasTrap = mHasEX || mHasIR 107 private val hsHasTrap = hsHasEX || hsHasIR 108 private val vsHasTrap = vsHasEX || vsHasIR 109 110 private val handleTrapUnderHS = !privState.isModeM && hsHasTrap 111 private val handleTrapUnderVS = privState.isVirtual && vsHasTrap 112 113 // Todo: support more interrupt and exception 114 private val exceptionRegular = OHToUInt(highestPrioEX) 115 private val interruptNO = OHToUInt(Mux(hasNMI, highestPrioNMI, highestPrioIR)) 116 private val exceptionNO = Mux(trapInfo.bits.singleStep, ExceptionNO.breakPoint.U, exceptionRegular) 117 118 private val causeNO = Mux(hasIR, interruptNO, exceptionNO) 119 120 private val xtvec = MuxCase(io.in.mtvec, Seq( 121 handleTrapUnderVS -> io.in.vstvec, 122 handleTrapUnderHS -> io.in.stvec 123 )) 124 private val pcFromXtvec = Cat(xtvec.addr.asUInt + Mux(xtvec.mode === XtvecMode.Vectored && hasIR, interruptNO(5, 0), 0.U), 0.U(2.W)) 125 126 io.out.entryPrivState := MuxCase(default = PrivState.ModeM, mapping = Seq( 127 handleTrapUnderVS -> PrivState.ModeVS, 128 handleTrapUnderHS -> PrivState.ModeHS, 129 )) 130 131 io.out.causeNO.Interrupt := hasIR 132 io.out.causeNO.ExceptionCode := causeNO 133 io.out.pcFromXtvec := pcFromXtvec 134 135 def filterIRQs(group: Seq[Int], originIRQ: UInt): Seq[Bool] = { 136 group.map(irqNum => originIRQ(irqNum)) 137 } 138 139 def getIRQHigherThanInGroup(group: Seq[Int])(irq: Int): Seq[Int] = { 140 val idx = group.indexOf(irq, 0) 141 require(idx != -1, s"The irq($irq) does not exists in IntPriority Seq") 142 group.slice(0, idx) 143 } 144 145 def getMaskFromIRQGroup(group: Seq[Int]): UInt = { 146 group.map(irq => BigInt(1) << irq).reduce(_ | _).U 147 } 148 149 def produceHighIRInGroup(irqGroup: Seq[Int], filteredIRVec: UInt): Vec[Bool] = { 150 val irVec = Wire(Vec(64, Bool())) 151 irVec.zipWithIndex.foreach { case (irq, i) => 152 if (irqGroup.contains(i)) { 153 val higherIRSeq: Seq[Int] = getIRQHigherThanInGroup(irqGroup)(i) 154 irq := ( 155 higherIRSeq.nonEmpty.B && Cat(higherIRSeq.map(num => !filteredIRVec(num))).andR || 156 higherIRSeq.isEmpty.B 157 ) && filteredIRVec(i) 158 } else 159 irq := false.B 160 } 161 irVec 162 } 163} 164 165class TrapHandleIO extends Bundle { 166 val in = Input(new Bundle { 167 val trapInfo = ValidIO(new Bundle { 168 val trapVec = UInt(64.W) 169 val nmi = Bool() 170 val intrVec = UInt(64.W) 171 val isInterrupt = Bool() 172 val singleStep = Bool() 173 }) 174 val privState = new PrivState 175 val mideleg = new MidelegBundle 176 val medeleg = new MedelegBundle 177 val hideleg = new HidelegBundle 178 val hedeleg = new HedelegBundle 179 val mvien = new MvienBundle 180 val hvien = new HvienBundle 181 // trap vector 182 val mtvec = Input(new XtvecBundle) 183 val stvec = Input(new XtvecBundle) 184 val vstvec = Input(new XtvecBundle) 185 }) 186 187 val out = new Bundle { 188 val entryPrivState = new PrivState 189 val causeNO = new CauseBundle 190 val pcFromXtvec = UInt() 191 } 192}