xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala (revision 01cdded87283f55be427ca849d18baa3e9459c2d) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import CSRConfig._
6import xiangshan.backend.fu.NewCSR.CSRDefines._
7import xiangshan.backend.fu.NewCSR.CSRDefines.{
8  CSRWARLField => WARL,
9  CSRRWField => RW,
10  CSRROField => RO,
11}
12import xiangshan.backend.fu.NewCSR.CSRFunc._
13
14import scala.collection.immutable.SeqMap
15
16trait DebugLevel { self: NewCSR =>
17  val dcsr = Module(new CSRModule("dcsr", new DcsrBundle))
18    .setAddr(0x7B0)
19
20  val dpc = Module(new CSRModule("dpc", new Dpc))
21    .setAddr(0x7B1)
22
23  val dscratch0 = Module(new CSRModule("dscratch0"))
24    .setAddr(0x7B2)
25
26  val dscratch1 = Module(new CSRModule("dscratch1"))
27    .setAddr(0x7B3)
28
29  val debugCSRMods = Seq(
30    dcsr,
31    dpc,
32    dscratch0,
33    dscratch1,
34  )
35
36  val debugCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_ <: CSRBundle], UInt)] = SeqMap.from(
37    debugCSRMods.map(csr => csr.addr -> (csr.w -> csr.rdata.asInstanceOf[CSRBundle].asUInt)).iterator
38  )
39
40  val debugCSROutMap: SeqMap[Int, UInt] = SeqMap.from(
41    debugCSRMods.map(csr => csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt).iterator
42  )
43}
44
45class DcsrBundle extends CSRBundle {
46  val DEBUGVER  = DcsrDebugVer(31, 28).withReset(DcsrDebugVer.Spec) // Debug implementation as it described in 0.13 draft // todo
47  // All ebreak Privileges are RW, instead of WARL, since XiangShan support U/S/VU/VS.
48  val EBREAKVS  =           RW(    17).withReset(0.U)
49  val EBREAKVU  =           RW(    16).withReset(0.U)
50  val EBREAKM   =           RW(    15).withReset(0.U)
51  val EBREAKS   =           RW(    13).withReset(0.U)
52  val EBREAKU   =           RW(    12).withReset(0.U)
53  // STEPIE is RW, instead of WARL, since XiangShan support interrupts being enabled single stepping.
54  val STEPIE    =           RW(    11).withReset(0.U)
55  val STOPCOUNT =           RO(    10).withReset(0.U) // Stop count updating has not been supported
56  val STOPTIME  =           RO(     9).withReset(0.U) // Stop time updating has not been supported
57  val CAUSE     =    DcsrCause( 8,  6).withReset(DcsrCause.none)
58  val V         =     VirtMode(     5).withReset(VirtMode.Off)
59  // MPRVEN is RW, instead of WARL, since XiangShan support use mstatus.mprv in debug mode
60  // Whether use mstatus.mprv
61  val MPRVEN    =           RW(     4).withReset(0.U)
62  // TODO: support non-maskable interrupt
63  val NMIP      =           RO(     3).withReset(0.U)
64  // MPRVEN is RW, instead of WARL, since XiangShan support use mstatus.mprv in debug mode
65  val STEP      =           RW(     2).withReset(0.U)
66  val PRV       =     PrivMode( 1,  0).withReset(PrivMode.M)
67}
68
69class Dpc extends CSRBundle {
70  val ALL = RW(63, 1)
71}
72
73object DcsrDebugVer extends CSREnum with ROApply {
74  val None = Value(0.U)
75  val Spec = Value(4.U)
76  val Custom = Value(15.U)
77}
78
79object DcsrCause extends CSREnum with ROApply {
80  val none         = Value(0.U)
81  val ebreak       = Value(1.U)
82  val trigger      = Value(2.U)
83  val haltreq      = Value(3.U)
84  val step         = Value(4.U)
85  val resethaltreq = Value(5.U)
86  val group        = Value(6.U)
87}
88