1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.{SignExt, ZeroExt} 7import xiangshan.{ExceptionNO, HasXSParameter, TriggerAction} 8import xiangshan.ExceptionNO._ 9import xiangshan.backend.fu.NewCSR 10import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 11import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 12import xiangshan.backend.fu.NewCSR.CSRDefines.SatpMode 13import xiangshan.backend.fu.NewCSR._ 14 15 16class TrapEntryDEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 17 val dcsr = ValidIO((new DcsrBundle).addInEvent(_.CAUSE, _.V, _.PRV)) 18 val dpc = ValidIO((new Epc ).addInEvent(_.epc)) 19 val targetPc = ValidIO(new TargetPCBundle) 20 val debugMode = ValidIO(Bool()) 21 val debugIntrEnable = ValidIO(Bool()) 22} 23 24class TrapEntryDEventInput(implicit override val p: Parameters) extends TrapEntryEventInput{ 25 val hasTrap = Input(Bool()) 26 val debugMode = Input(Bool()) 27 val hasDebugIntr = Input(Bool()) 28 val triggerEnterDebugMode = Input(Bool()) 29 val hasDebugEbreakException = Input(Bool()) 30 val hasSingleStep = Input(Bool()) 31 val breakPoint = Input(Bool()) 32} 33 34class TrapEntryDEventModule(implicit val p: Parameters) extends Module with CSREventBase with DebugMMIO { 35 val in = IO(new TrapEntryDEventInput) 36 val out = IO(new TrapEntryDEventOutput) 37 38 private val current = in 39 private val iMode = current.iMode 40 private val satp = current.satp 41 private val vsatp = current.vsatp 42 private val hgatp = current.hgatp 43 44 private val hasTrap = in.hasTrap 45 private val debugMode = in.debugMode 46 private val hasDebugIntr = in.hasDebugIntr 47 private val breakPoint = in.breakPoint 48 private val triggerEnterDebugMode = in.triggerEnterDebugMode 49 private val hasDebugEbreakException = in.hasDebugEbreakException 50 private val hasSingleStep = in.hasSingleStep 51 52 private val hasExceptionInDmode = debugMode && hasTrap 53 val causeIntr = DcsrCause.Haltreq.asUInt 54 val causeExp = MuxCase(0.U, Seq( 55 triggerEnterDebugMode -> DcsrCause.Trigger.asUInt, 56 hasDebugEbreakException -> DcsrCause.Ebreak.asUInt, 57 hasSingleStep -> DcsrCause.Step.asUInt 58 )) 59 60 private val trapPC = genTrapVA( 61 iMode, 62 satp, 63 vsatp, 64 hgatp, 65 in.trapPc, 66 ) 67 68 // ebreak jump debugEntry not debugException in dmode 69 // debug rom make hart write 0 to DebugMMIO.EXCEPTION when exception happened in debugMode. 70 // let debug module known hart got an exception. 71 // note: Need't know exception number in debugMode. 72 // exception(EX_BP) must be ebreak here! 73 val debugPc = Mux(hasExceptionInDmode && !breakPoint, DebugException.U, DebugEntry.U) 74 75 out := DontCare 76 // output 77 out.dcsr.valid := valid 78 out.dpc.valid := valid 79 // !debugMode trap || debugMode hasExp 80 out.targetPc.valid := valid || hasExceptionInDmode 81 out.debugMode.valid := valid 82 out.privState.valid := valid 83 out.debugIntrEnable.valid := valid 84 85 out.dcsr.bits.V := current.privState.V.asUInt 86 out.dcsr.bits.PRV := current.privState.PRVM.asUInt 87 out.dcsr.bits.CAUSE := Mux(hasDebugIntr, causeIntr, causeExp) 88 out.dpc.bits.epc := trapPC(63, 1) 89 90 out.targetPc.bits.pc := debugPc 91 out.targetPc.bits.raiseIPF := false.B 92 out.targetPc.bits.raiseIAF := false.B 93 out.targetPc.bits.raiseIGPF := false.B 94 out.debugMode.bits := true.B 95 out.privState.bits := PrivState.ModeM 96 out.debugIntrEnable.bits := false.B 97 98} 99 100trait TrapEntryDEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 101 val trapToD = IO(Flipped(new TrapEntryDEventOutput)) 102 103 addUpdateBundleInCSREnumType(trapToD.getBundleByName(self.modName.toLowerCase())) 104 105 reconnectReg() 106} 107