1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.{SignExt, ZeroExt} 7import xiangshan.ExceptionNO 8import xiangshan.ExceptionNO._ 9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 10import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 11import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, PrivMode, SatpMode, VirtMode} 12import xiangshan.backend.fu.NewCSR._ 13import xiangshan.AddrTransType 14 15 16class MretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 17 val mstatus = ValidIO((new MstatusBundle).addInEvent(_.MPP, _.MPV, _.MIE, _.MPIE, _.MPRV)) 18 val tcontrol = ValidIO((new TcontrolBundle).addInEvent(_.MTE)) 19 val targetPc = ValidIO(new TargetPCBundle) 20 21 override def getBundleByName(name: String): ValidIO[CSRBundle] = { 22 name match { 23 case "mstatus" => this.mstatus 24 case "tcontrol" => this.tcontrol 25 } 26 } 27} 28 29class MretEventInput extends Bundle { 30 val mstatus = Input(new MstatusBundle) 31 val mepc = Input(new Epc()) 32 val tcontrol = Input(new TcontrolBundle) 33 val satp = Input(new SatpBundle) 34 val vsatp = Input(new SatpBundle) 35 val hgatp = Input(new HgatpBundle) 36} 37 38class MretEventModule(implicit p: Parameters) extends Module with CSREventBase { 39 val in = IO(new MretEventInput) 40 val out = IO(new MretEventOutput) 41 42 private val satp = in.satp 43 private val vsatp = in.vsatp 44 private val hgatp = in.hgatp 45 private val nextPrivState = out.privState.bits 46 47 private val instrAddrTransType = AddrTransType( 48 bare = nextPrivState.isModeM || 49 (!nextPrivState.isVirtual && satp.MODE === SatpMode.Bare) || 50 (nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare), 51 sv39 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv39 || 52 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv39, 53 sv48 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv48 || 54 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv48, 55 sv39x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4, 56 sv48x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4 57 ) 58 59 out := DontCare 60 61 out.privState.valid := valid 62 out.mstatus .valid := valid 63 out.tcontrol .valid := valid 64 out.targetPc .valid := valid 65 66 out.privState.bits.PRVM := in.mstatus.MPP 67 out.privState.bits.V := Mux(in.mstatus.MPP === PrivMode.M, VirtMode.Off.asUInt, in.mstatus.MPV.asUInt) 68 out.mstatus.bits.MPP := PrivMode.U 69 out.mstatus.bits.MPV := VirtMode.Off.asUInt 70 out.mstatus.bits.MIE := in.mstatus.MPIE 71 out.mstatus.bits.MPIE := 1.U 72 out.mstatus.bits.MPRV := Mux(in.mstatus.MPP =/= PrivMode.M, 0.U, in.mstatus.MPRV.asUInt) 73 out.tcontrol.bits.MTE := in.tcontrol.MPTE 74 out.targetPc.bits.pc := in.mepc.asUInt 75 out.targetPc.bits.raiseIPF := instrAddrTransType.checkPageFault(in.mepc.asUInt) 76 out.targetPc.bits.raiseIAF := instrAddrTransType.checkAccessFault(in.mepc.asUInt) 77 out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.mepc.asUInt) 78} 79 80trait MretEventSinkBundle { self: CSRModule[_] => 81 val retFromM = IO(Flipped(new MretEventOutput)) 82 83 private val updateBundle: ValidIO[CSRBundle] = retFromM.getBundleByName(self.modName.toLowerCase()) 84 85 (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) => 86 if (updateBundle.bits.eventFields.contains(source)) { 87 when(updateBundle.valid) { 88 sink := source 89 } 90 } 91 } 92 93} 94