1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.{SignExt, ZeroExt} 7import xiangshan.ExceptionNO 8import xiangshan.ExceptionNO._ 9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 10import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 11import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, PrivMode, SatpMode, VirtMode} 12import xiangshan.backend.fu.NewCSR._ 13import xiangshan.AddrTransType 14 15 16class MretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 17 val mstatus = ValidIO((new MstatusBundle).addInEvent(_.MPP, _.MPV, _.MIE, _.MPIE, _.MPRV)) 18 val targetPc = ValidIO(new TargetPCBundle) 19} 20 21class MretEventInput extends Bundle { 22 val mstatus = Input(new MstatusBundle) 23 val mepc = Input(new Epc()) 24 val satp = Input(new SatpBundle) 25 val vsatp = Input(new SatpBundle) 26 val hgatp = Input(new HgatpBundle) 27} 28 29class MretEventModule(implicit p: Parameters) extends Module with CSREventBase { 30 val in = IO(new MretEventInput) 31 val out = IO(new MretEventOutput) 32 33 private val satp = in.satp 34 private val vsatp = in.vsatp 35 private val hgatp = in.hgatp 36 private val nextPrivState = out.privState.bits 37 38 private val instrAddrTransType = AddrTransType( 39 bare = nextPrivState.isModeM || 40 (!nextPrivState.isVirtual && satp.MODE === SatpMode.Bare) || 41 (nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare), 42 sv39 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv39 || 43 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv39, 44 sv48 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv48 || 45 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv48, 46 sv39x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4, 47 sv48x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4 48 ) 49 50 out := DontCare 51 52 out.privState.valid := valid 53 out.mstatus .valid := valid 54 out.targetPc .valid := valid 55 56 out.privState.bits.PRVM := in.mstatus.MPP 57 out.privState.bits.V := Mux(in.mstatus.MPP === PrivMode.M, VirtMode.Off.asUInt, in.mstatus.MPV.asUInt) 58 out.mstatus.bits.MPP := PrivMode.U 59 out.mstatus.bits.MPV := VirtMode.Off.asUInt 60 out.mstatus.bits.MIE := in.mstatus.MPIE 61 out.mstatus.bits.MPIE := 1.U 62 out.mstatus.bits.MPRV := Mux(in.mstatus.MPP =/= PrivMode.M, 0.U, in.mstatus.MPRV.asUInt) 63 out.targetPc.bits.pc := in.mepc.asUInt 64 out.targetPc.bits.raiseIPF := instrAddrTransType.checkPageFault(in.mepc.asUInt) 65 out.targetPc.bits.raiseIAF := instrAddrTransType.checkAccessFault(in.mepc.asUInt) 66 out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.mepc.asUInt) 67} 68 69trait MretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 70 val retFromM = IO(Flipped(new MretEventOutput)) 71 72 addUpdateBundleInCSREnumType(retFromM.getBundleByName(self.modName.toLowerCase())) 73 74 reconnectReg() 75} 76