xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala (revision c08f49a0dbf6e9ef292ad0b90193d3946d11b1b6) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.ExceptionNO
8import xiangshan.ExceptionNO._
9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState}
10import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN}
11import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, PrivMode, SatpMode, VirtMode}
12import xiangshan.backend.fu.NewCSR._
13import xiangshan.AddrTransType
14
15
16class MNretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase {
17  val mnstatus  = ValidIO((new MnstatusBundle).addInEvent(_.MNPP, _.MNPV, _.NMIE))
18  val mstatus   = ValidIO((new MstatusBundle).addInEvent(_.MPRV))
19  val targetPc  = ValidIO(new TargetPCBundle)
20}
21
22class MNretEventInput extends Bundle {
23  val mnstatus = Input(new MnstatusBundle)
24  val mstatus  = Input(new MstatusBundle)
25  val mnepc    = Input(new Epc())
26  val satp     = Input(new SatpBundle)
27  val vsatp    = Input(new SatpBundle)
28  val hgatp    = Input(new HgatpBundle)
29}
30
31class MNretEventModule(implicit p: Parameters) extends Module with CSREventBase {
32  val in = IO(new MNretEventInput)
33  val out = IO(new MNretEventOutput)
34
35  private val satp = in.satp
36  private val vsatp = in.vsatp
37  private val hgatp = in.hgatp
38  private val nextPrivState = out.privState.bits
39
40  private val instrAddrTransType = AddrTransType(
41    bare = nextPrivState.isModeM ||
42           (!nextPrivState.isVirtual && satp.MODE === SatpMode.Bare) ||
43           (nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare),
44    sv39 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv39 ||
45           nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv39,
46    sv48 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv48 ||
47           nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv48,
48    sv39x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4,
49    sv48x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4
50  )
51
52  out := DontCare
53
54  out.privState.valid := valid
55  out.mnstatus .valid := valid
56  out.targetPc .valid := valid
57
58  out.privState.bits.PRVM     := in.mnstatus.MNPP
59  out.privState.bits.V        := Mux(in.mnstatus.MNPP === PrivMode.M, VirtMode.Off.asUInt, in.mnstatus.MNPV.asUInt)
60  out.mnstatus.bits.MNPP      := PrivMode.U
61  out.mnstatus.bits.MNPV      := VirtMode.Off.asUInt
62  out.mnstatus.bits.NMIE      := 1.U
63  out.mstatus.bits.MPRV       := Mux(in.mnstatus.MNPP =/= PrivMode.M, 0.U, in.mstatus.MPRV.asUInt)
64  out.targetPc.bits.pc        := in.mnepc.asUInt
65  out.targetPc.bits.raiseIPF  := instrAddrTransType.checkPageFault(in.mnepc.asUInt)
66  out.targetPc.bits.raiseIAF  := instrAddrTransType.checkAccessFault(in.mnepc.asUInt)
67  out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.mnepc.asUInt)
68}
69
70trait MNretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
71  val retFromMN = IO(Flipped(new MNretEventOutput))
72
73  addUpdateBundleInCSREnumType(retFromMN.getBundleByName(self.modName.toLowerCase()))
74
75  reconnectReg()
76}