1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import xiangshan.backend.fu.NewCSR.CSRConfig.VaddrMaxWidth 7import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, PrivMode, SatpMode} 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.AddrTransType 10 11 12class DretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 13 val dcsr = ValidIO((new DcsrBundle).addInEvent(_.V, _.PRV)) 14 val mstatus = ValidIO((new MstatusBundle).addInEvent(_.MPRV)) 15 val debugMode = ValidIO(Bool()) 16 val debugIntrEnable = ValidIO(Bool()) 17 val targetPc = ValidIO(new TargetPCBundle) 18 19 override def getBundleByName(name: String): ValidIO[CSRBundle] = { 20 name match { 21 case "dcsr" => this.dcsr 22 case "mstatus" => this.mstatus 23 } 24 } 25} 26 27class DretEventInput extends Bundle { 28 val dcsr = Input(new DcsrBundle) 29 val dpc = Input(new Epc) 30 val mstatus = Input(new MstatusBundle) 31 val satp = Input(new SatpBundle) 32 val vsatp = Input(new SatpBundle) 33 val hgatp = Input(new HgatpBundle) 34} 35 36class DretEventModule(implicit p: Parameters) extends Module with CSREventBase { 37 val in = IO(new DretEventInput) 38 val out = IO(new DretEventOutput) 39 40 private val satp = in.satp 41 private val vsatp = in.vsatp 42 private val hgatp = in.hgatp 43 private val nextPrivState = out.privState.bits 44 45 private val instrAddrTransType = AddrTransType( 46 bare = nextPrivState.isModeM || 47 (!nextPrivState.isVirtual && satp.MODE === SatpMode.Bare) || 48 (nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare), 49 sv39 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv39 || 50 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv39, 51 sv48 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv48 || 52 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv48, 53 sv39x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4, 54 sv48x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4 55 ) 56 57 out := DontCare 58 59 out.debugMode.valid := valid 60 out.privState.valid := valid 61 out.dcsr.valid := valid 62 out.mstatus.valid := valid 63 out.debugIntrEnable.valid := valid 64 out.targetPc.valid := valid 65 66 out.privState.bits.PRVM := in.dcsr.PRV.asUInt 67 out.privState.bits.V := in.dcsr.V 68 out.mstatus.bits.MPRV := Mux(!out.privState.bits.isModeM, 0.U, in.mstatus.MPRV.asUInt) 69 out.debugMode.bits := false.B 70 out.debugIntrEnable.bits := true.B 71 out.targetPc.bits.pc := in.dpc.asUInt 72 out.targetPc.bits.raiseIPF := instrAddrTransType.checkPageFault(in.dpc.asUInt) 73 out.targetPc.bits.raiseIAF := instrAddrTransType.checkAccessFault(in.dpc.asUInt) 74 out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.dpc.asUInt) 75} 76 77trait DretEventSinkBundle { self: CSRModule[_] => 78 val retFromD = IO(Flipped(new DretEventOutput)) 79 80 private val updateBundle: ValidIO[CSRBundle] = retFromD.getBundleByName(self.modName.toLowerCase()) 81 82 (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case(sink, source) => 83 if (updateBundle.bits.eventFields.contains(source)) { 84 when(updateBundle.valid) { 85 sink := source 86 } 87 } 88 } 89} 90