xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala (revision 01cdded87283f55be427ca849d18baa3e9459c2d) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import freechips.rocketchip.util._
6import org.chipsalliance.cde.config.Parameters
7import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRRWField => RW}
8import xiangshan.HasXSParameter
9
10import scala.collection.immutable.SeqMap
11
12trait CSRCustom { self: NewCSR =>
13  // Supervisor Custom Read/Write
14  val sbpctl = Module(new CSRModule("sbpctl", new SbpctlBundle))
15    .setAddr(0x5C0)
16
17  val spfctl = Module(new CSRModule("spfctl", new SpfctlBundle))
18    .setAddr(0x5C1)
19
20  // slvpredctl: load violation predict settings
21  // Default reset period: 2^16
22  // why this number: reset more frequently while keeping the overhead low
23  // Overhead: extra two redirections in every 64K cycles => ~0.1% overhead
24  val slvpredctl = Module(new CSRModule("slvpredctl", new SlvpredctlBundle))
25    .setAddr(0x5C2)
26
27  // smblockctl: memory block configurations
28  val smblockctl = Module(new CSRModule("smblockctl", new SmblockctlBundle))
29    .setAddr(0x5C3)
30
31  val srnctl = Module(new CSRModule("srnctl", new SrnctlBundle))
32    .setAddr(0x5C4)
33
34  // sdsid: Differentiated Services ID
35  val sdsid = Module(new CSRModule("sdsid"))
36    .setAddr(0x9C0)
37
38  val sfetchctl = Module(new CSRModule("sfetchctl", new SfetchctlBundle))
39    .setAddr(0x9E0)
40
41  val customCSRMods = Seq(
42    sbpctl,
43    spfctl,
44    slvpredctl,
45    smblockctl,
46    srnctl,
47    sdsid,
48    sfetchctl,
49  )
50
51  val customCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_ <: CSRBundle], Data)] = SeqMap.from(
52    customCSRMods.map(csr => (csr.addr -> (csr.w -> csr.rdata.asInstanceOf[CSRBundle].asUInt))).iterator
53  )
54
55  val customCSROutMap: SeqMap[Int, UInt] = SeqMap.from(
56    customCSRMods.map(csr => (csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt)).iterator
57  )
58}
59
60class SbpctlBundle extends CSRBundle {
61  val LOOP_ENABLE = RW(6).withReset(true.B)
62  val RAS_ENABLE  = RW(5).withReset(true.B)
63  val SC_ENABLE   = RW(4).withReset(true.B)
64  val TAGE_ENABLE = RW(3).withReset(true.B)
65  val BIM_ENABLE  = RW(2).withReset(true.B)
66  val BTB_ENABLE  = RW(1).withReset(true.B)
67  val UBTB_ENABLE = RW(0).withReset(true.B)
68}
69
70class SpfctlBundle extends CSRBundle {
71  // turn off L2 BOP, turn on L1 SMS by default
72  val L2_PF_STORE_ONLY        = RW(    17).withReset(false.B)     // L2 pf store only
73  val L1D_PF_ENABLE_STRIDE    = RW(    16).withReset(true.B)      // L1D prefetch enable stride
74  val L1D_PF_ACTIVE_STRIDE    = RW(15, 10, /*resetVal= */ 30.U)   // L1D prefetch active page stride
75  val L1D_PF_ACTIVE_THRESHOLD = RW( 9,  6, /*resetVal= */ 12.U)   // L1D prefetch active page threshold
76  val L1D_PF_ENABLE_PHT       = RW(     5).withReset(true.B)      // L1D prefetch enable pht
77  val L1D_PF_ENABLE_AGT       = RW(     4).withReset(true.B)      // L1D prefetch enable agt
78  val L1D_PF_TRAIN_ON_HIT     = RW(     3).withReset(false.B)     // L1D train prefetch on hit
79  val L1D_PF_ENABLE           = RW(     2).withReset(true.B)      // L1D Cache Prefetcher Enable
80  val L2_PF_ENABLE            = RW(     1).withReset(true.B)      // L2  Cache Prefetcher Enable
81  val L1I_PF_ENABLE           = RW(     0).withReset(true.B)      // L1I Cache Prefetcher Enable
82}
83
84class SlvpredctlBundle extends CSRBundle {
85  val LVPRED_TIMEOUT          = RW(8, 4, /*resetVal= */ 3.U)
86  val STORESET_NO_FAST_WAKEUP = RW(3).withReset(0.U)
87  val STORESET_WAIT_STORE     = RW(2).withReset(0.U)
88  val NO_SPEC_LOAD            = RW(1).withReset(0.U)
89  val LVPRED_DISABLE          = RW(0).withReset(0.U)
90}
91
92class SmblockctlBundle extends CSRBundle {
93  val UNCACHE_WRITE_OUTSTANDING_ENABLE = RW(   7).withReset(0.U) // Enable uncache write outstanding (0). Todo:
94  val CACHE_ERROR_ENABLE               = RW(   6)                // Enable cache error after reset (CE).
95  val SOFT_PREFETCH_ENABLE             = RW(   5)                // Enable soft-prefetch after reset (SP).
96  val LDLD_VIO_CHECK_ENABLE            = RW(   4)                // Enable load load violation check after reset (LVC).
97  val SBUFFER_THRESHOLD                = RW(3, 0)                // Store buffer flush threshold (Th).
98}
99
100class SrnctlBundle extends CSRBundle {
101  val WFI_ENABLE     = RW(2).withReset(true.B)
102  val SVINVAL_ENABLE = RW(1).withReset(true.B)
103  val FUSION_ENABLE  = RW(0).withReset(true.B)
104}
105
106class SfetchctlBundle extends CSRBundle {
107  val ICACHE_PARITY_ENABLE = RW(0).withReset(false.B) // L1I Cache Parity check enable
108}