1package xiangshan.backend.fu 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7import xiangshan.backend._ 8import xiangshan.backend.fu.FunctionUnit._ 9import xiangshan.backend.decode.isa._ 10 11trait HasRedirectOut { this: RawModule => 12 val redirectOutValid = IO(Output(Bool())) 13 val redirectOut = IO(Output(new Redirect)) 14 val brUpdate = IO(Output(new CfiUpdateInfo)) 15} 16 17class Jump extends FunctionUnit with HasRedirectOut { 18 19 val (src1, offset, func, pc, uop) = ( 20 io.in.bits.src(0), 21 io.in.bits.uop.ctrl.imm, 22 io.in.bits.uop.ctrl.fuOpType, 23 SignExt(io.in.bits.uop.cf.pc, AddrBits), 24 io.in.bits.uop 25 ) 26 27 val redirectHit = uop.roqIdx.needFlush(io.redirectIn) 28 val valid = io.in.valid 29 30 val isRVC = uop.cf.brUpdate.pd.isRVC 31 val snpc = Mux(isRVC, pc + 2.U, pc + 4.U) 32 val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 33 34 redirectOutValid := valid 35 redirectOut.pc := uop.cf.pc 36 redirectOut.target := target 37 redirectOut.brTag := uop.brTag 38 redirectOut.level := RedirectLevel.flushAfter 39 redirectOut.interrupt := DontCare 40 redirectOut.roqIdx := uop.roqIdx 41 42 brUpdate := uop.cf.brUpdate 43 brUpdate.pc := uop.cf.pc 44 brUpdate.target := target 45 brUpdate.brTarget := target 46 brUpdate.taken := true.B 47 48 // Output 49 val res = snpc 50 51 io.in.ready := io.out.ready 52 io.out.valid := valid 53 io.out.bits.uop <> io.in.bits.uop 54 io.out.bits.data := res 55 56 // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 57 XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x\n", 58 io.in.valid, 59 io.in.ready, 60 io.out.valid, 61 io.out.ready, 62 io.redirectIn.valid, 63 io.redirectIn.bits.level, 64 redirectHit, 65 io.redirectIn.bits.brTag.value 66 ) 67 XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res) 68} 69