1package xiangshan.backend.fu 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7import xiangshan.backend._ 8import xiangshan.backend.fu.FunctionUnit._ 9import xiangshan.backend.decode.isa._ 10 11trait HasRedirectOut { this: RawModule => 12 val redirectOutValid = IO(Output(Bool())) 13 val redirectOut = IO(Output(new Redirect)) 14 val brUpdate = IO(Output(new BranchUpdateInfo)) 15} 16 17class Jump extends FunctionUnit( 18 FuConfig(FuType.jmp, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true) 19) with HasRedirectOut { 20 21 val (src1, offset, func, pc, uop) = ( 22 io.in.bits.src(0), 23 io.in.bits.uop.ctrl.imm, 24 io.in.bits.uop.ctrl.fuOpType, 25 SignExt(io.in.bits.uop.cf.pc, AddrBits), 26 io.in.bits.uop 27 ) 28 29 val redirectHit = uop.roqIdx.needFlush(io.redirectIn) 30 val valid = io.in.valid && !redirectHit 31 32 val isRVC = uop.cf.brUpdate.pd.isRVC 33 val snpc = Mux(isRVC, pc + 2.U, pc + 4.U) 34 val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 35 36 redirectOutValid := valid 37 redirectOut.pc := uop.cf.pc 38 redirectOut.target := target 39 redirectOut.brTag := uop.brTag 40 redirectOut.isException := false.B 41 redirectOut.isFlushPipe := false.B 42 redirectOut.isMisPred := DontCare // check this in brq 43 redirectOut.isReplay := false.B 44 redirectOut.roqIdx := uop.roqIdx 45 46 brUpdate := uop.cf.brUpdate 47 brUpdate.pc := uop.cf.pc 48 brUpdate.target := target 49 brUpdate.brTarget := target // DontCare 50 brUpdate.taken := true.B 51 52 // Output 53 val res = snpc 54 55 io.in.ready := io.out.ready 56 io.out.valid := valid 57 io.out.bits.uop <> io.in.bits.uop 58 io.out.bits.data := res 59 60 // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 61 XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d %d) brTag:%x\n", 62 io.in.valid, 63 io.in.ready, 64 io.out.valid, 65 io.out.ready, 66 io.redirectIn.valid, 67 io.redirectIn.bits.isException, 68 io.redirectIn.bits.isFlushPipe, 69 redirectHit, 70 io.redirectIn.bits.brTag.value 71 ) 72 XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res) 73} 74