1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 writeVType : Boolean = false, 67 immType : Set[UInt] = Set(), 68 // vector 69 vconfigWakeUp : Boolean = false, 70 maskWakeUp : Boolean = false, 71) { 72 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 73 def needFpWen: Boolean = writeFpRf 74 def needVecWen: Boolean = writeVecRf 75 var vconfigIdx = -1 76 var maskSrcIdx = -1 77 if (vconfigWakeUp) { 78 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 79 } 80 if (maskWakeUp) { 81 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 82 } 83 84 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 85 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 86 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 87 88 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 89 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 93 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 94 95 def readFp: Boolean = numFpSrc > 0 96 97 def fuSel(uop: ExuInput): Bool = { 98 // Don't add more shit here!!! 99 // Todo: add new FuType to distinguish f2i, f2f 100 uop.fuType === this.fuType.U 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 138 139 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 140 141 // predict info 142 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 143 144 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 145 146 def needFPUCtrl: Boolean = { 147 import FuType._ 148 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 149 } 150 151 def needVecCtrl: Boolean = { 152 import FuType._ 153 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 154 } 155 156 def isMul: Boolean = fuType == FuType.mul 157 158 def isDiv: Boolean = fuType == FuType.div 159 160 def isCsr: Boolean = fuType == FuType.csr 161 162 def isFence: Boolean = fuType == FuType.fence 163 164 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 165 fuType == FuType.vppu || fuType == FuType.vipu || 166 fuType == FuType.vfalu || fuType == FuType.vfma || 167 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 168 fuType == FuType.vidiv 169 170 def needOg2: Boolean = isVecArith || fuType == FuType.fmisc || fuType == FuType.vsetfwf || fuType == FuType.f2v 171 172 def isSta: Boolean = name.contains("sta") 173 174 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 175 fuType == FuType.fmisc || fuType == FuType.div || 176 fuType == FuType.vfdiv || fuType == FuType.vidiv 177 178 /** 179 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 180 * @param data [[DataConfig]] 181 * @param tips tips if get failed 182 * @return the index of special src data 183 */ 184 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 185 val srcIdxVec = srcData.map(x => x.indexOf(data)) 186 val idx0 = srcIdxVec.head 187 for (idx <- srcIdxVec) { 188 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 189 } 190 idx0 191 } 192 193 override def toString: String = { 194 var str = s"${this.name}: " 195 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 196 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 197 str += s"latency($latency)" 198 str += s"src($srcData)" 199 str 200 } 201} 202 203object FuConfig { 204 val JmpCfg: FuConfig = FuConfig ( 205 name = "jmp", 206 fuType = FuType.jmp, 207 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 208 srcData = Seq( 209 Seq(IntData()), // jal 210 ), 211 piped = true, 212 writeIntRf = true, 213 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 214 ) 215 216 val BrhCfg: FuConfig = FuConfig ( 217 name = "brh", 218 fuType = FuType.brh, 219 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 220 srcData = Seq( 221 Seq(IntData(), IntData()), 222 ), 223 piped = true, 224 immType = Set(SelImm.IMM_SB), 225 ) 226 227 val I2fCfg: FuConfig = FuConfig ( 228 name = "i2f", 229 FuType.i2f, 230 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 231 srcData = Seq( 232 Seq(IntData()), 233 ), 234 piped = true, 235 writeFpRf = true, 236 writeFflags = true, 237 latency = CertainLatency(2), 238 needSrcFrm = true, 239 ) 240 241 val I2vCfg: FuConfig = FuConfig ( 242 name = "i2v", 243 FuType.i2v, 244 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 245 srcData = Seq( 246 Seq(IntData(), IntData()), 247 ), 248 piped = true, 249 writeVecRf = true, 250 writeFpRf = true, 251 latency = CertainLatency(0), 252 dataBits = 128, 253 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 254 ) 255 256 val F2vCfg: FuConfig = FuConfig ( 257 name = "f2v", 258 FuType.f2v, 259 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 260 srcData = Seq( 261 Seq(FpData(), FpData()), 262 Seq(FpData()), 263 ), 264 piped = true, 265 writeVecRf = true, 266 latency = CertainLatency(0), 267 dataBits = 128, 268 ) 269 270 val CsrCfg: FuConfig = FuConfig ( 271 name = "csr", 272 fuType = FuType.csr, 273 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 274 srcData = Seq( 275 Seq(IntData()), 276 ), 277 piped = true, 278 writeIntRf = true, 279 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 280 flushPipe = true, 281 ) 282 283 val AluCfg: FuConfig = FuConfig ( 284 name = "alu", 285 fuType = FuType.alu, 286 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 287 srcData = Seq( 288 Seq(IntData(), IntData()), 289 ), 290 piped = true, 291 writeIntRf = true, 292 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 293 ) 294 295 val MulCfg: FuConfig = FuConfig ( 296 name = "mul", 297 fuType = FuType.mul, 298 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 299 srcData = Seq( 300 Seq(IntData(), IntData()), 301 ), 302 piped = true, 303 writeIntRf = true, 304 latency = CertainLatency(2), 305 ) 306 307 val DivCfg: FuConfig = FuConfig ( 308 name = "div", 309 fuType = FuType.div, 310 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 311 srcData = Seq( 312 Seq(IntData(), IntData()), 313 ), 314 piped = false, 315 writeIntRf = true, 316 latency = UncertainLatency(), 317 hasInputBuffer = (true, 4, true) 318 ) 319 320 val FenceCfg: FuConfig = FuConfig ( 321 name = "fence", 322 FuType.fence, 323 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 324 srcData = Seq( 325 Seq(IntData(), IntData()), 326 ), 327 piped = true, 328 latency = CertainLatency(0), 329 exceptionOut = Seq(illegalInstr, virtualInstr), 330 flushPipe = true 331 ) 332 333 // Todo: split it to simple bitmap exu and complex bku 334 val BkuCfg: FuConfig = FuConfig ( 335 name = "bku", 336 fuType = FuType.bku, 337 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 338 srcData = Seq( 339 Seq(IntData(), IntData()), 340 ), 341 piped = true, 342 writeIntRf = true, 343 latency = CertainLatency(2), 344 ) 345 346 val VSetRvfWvfCfg: FuConfig = FuConfig( 347 name = "vsetrvfwvf", 348 fuType = FuType.vsetfwf, 349 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 350 srcData = Seq( 351 Seq(FpData(), FpData()), 352 ), 353 piped = true, 354 writeVecRf = true, 355 writeVType = true, 356 latency = CertainLatency(0), 357 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 358 ) 359 360 val VSetRiWvfCfg: FuConfig = FuConfig( 361 name = "vsetriwvf", 362 fuType = FuType.vsetiwf, 363 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 364 srcData = Seq( 365 Seq(IntData(), IntData()), 366 ), 367 piped = true, 368 writeVecRf = true, 369 writeVType = true, 370 latency = CertainLatency(0), 371 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 372 ) 373 374 val VSetRiWiCfg: FuConfig = FuConfig( 375 name = "vsetriwi", 376 fuType = FuType.vsetiwi, 377 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 378 srcData = Seq( 379 Seq(IntData(), IntData()), 380 ), 381 piped = true, 382 writeIntRf = true, 383 latency = CertainLatency(0), 384 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 385 ) 386 387 val FmacCfg: FuConfig = FuConfig ( 388 name = "fmac", 389 fuType = FuType.fmac, 390 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 391 srcData = Seq( 392 Seq(FpData(), FpData()), 393 Seq(FpData(), FpData(), FpData()), 394 ), 395 piped = false, 396 writeFpRf = true, 397 writeFflags = true, 398 latency = UncertainLatency(), 399 needSrcFrm = true, 400 ) 401 402 val F2iCfg: FuConfig = FuConfig ( 403 name = "f2i", 404 fuType = FuType.fmisc, 405 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 406 srcData = Seq( 407 Seq(FpData(), FpData()), 408 Seq(FpData()), 409 ), 410 piped = true, 411 writeIntRf = true, 412 writeFflags = true, 413 latency = CertainLatency(2), 414 needSrcFrm = true, 415 ) 416 417 val F2fCfg: FuConfig = FuConfig ( 418 name = "f2f", 419 fuType = FuType.fmisc, 420 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 421 srcData = Seq( 422 Seq(FpData(), FpData()), 423 Seq(FpData()), 424 ), 425 piped = true, 426 writeFpRf = true, 427 writeFflags = true, 428 latency = CertainLatency(2), 429 needSrcFrm = true, 430 ) 431 432 val FDivSqrtCfg: FuConfig = FuConfig ( 433 name = "fDivSqrt", 434 fuType = FuType.fDivSqrt, 435 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 436 srcData = Seq( 437 Seq(FpData(), FpData()), 438 ), 439 piped = false, 440 writeFpRf = true, 441 writeFflags = true, 442 latency = UncertainLatency(), 443 hasInputBuffer = (true, 8, true), 444 needSrcFrm = true, 445 ) 446 447 val LduCfg: FuConfig = FuConfig ( 448 name = "ldu", 449 fuType = FuType.ldu, 450 fuGen = null, // Todo 451 srcData = Seq( 452 Seq(IntData()), 453 ), 454 piped = false, // Todo: check it 455 writeIntRf = true, 456 writeFpRf = true, 457 latency = UncertainLatency(3), 458 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 459 flushPipe = true, 460 replayInst = true, 461 hasLoadError = true, 462 trigger = true, 463 immType = Set(SelImm.IMM_I), 464 ) 465 466 val StaCfg: FuConfig = FuConfig ( 467 name = "sta", 468 fuType = FuType.stu, 469 fuGen = null, // Todo 470 srcData = Seq( 471 Seq(IntData()), 472 ), 473 piped = false, 474 latency = UncertainLatency(), 475 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 476 trigger = true, 477 immType = Set(SelImm.IMM_S), 478 ) 479 480 val StdCfg: FuConfig = FuConfig ( 481 name = "std", 482 fuType = FuType.stu, 483 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 484 srcData = Seq( 485 Seq(IntData()), 486 Seq(FpData()), 487 ), 488 piped = true, 489 latency = CertainLatency(0) 490 ) 491 492 val HyldaCfg = FuConfig ( 493 name = "hylda", 494 fuType = FuType.ldu, 495 fuGen = null, // Todo 496 srcData = Seq( 497 Seq(IntData()), 498 ), 499 piped = false, // Todo: check it 500 writeIntRf = true, 501 writeFpRf = true, 502 latency = UncertainLatency(3), 503 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 504 flushPipe = true, 505 replayInst = true, 506 hasLoadError = true, 507 immType = Set(SelImm.IMM_I), 508 ) 509 510 val HystaCfg = FuConfig ( 511 name = "hysta", 512 fuType = FuType.stu, 513 fuGen = null, // Todo 514 srcData = Seq( 515 Seq(IntData()), 516 ), 517 piped = false, 518 latency = UncertainLatency(), 519 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 520 immType = Set(SelImm.IMM_S), 521 ) 522 523 val FakeHystaCfg = FuConfig ( 524 name = "hysta", 525 fuType = FuType.stu, 526 fuGen = null, // Todo 527 srcData = Seq(), 528 piped = false, 529 latency = UncertainLatency(), 530 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 531 immType = Set(), 532 ) 533 534 val MouCfg: FuConfig = FuConfig ( 535 name = "mou", 536 fuType = FuType.mou, 537 fuGen = null, // Todo 538 srcData = Seq( 539 Seq(IntData()), 540 ), 541 piped = false, // Todo: check it 542 writeFakeIntRf = true, 543 latency = UncertainLatency(), 544 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 545 trigger = true, 546 ) 547 548 val MoudCfg: FuConfig = FuConfig ( 549 name = "moud", 550 fuType = FuType.mou, 551 fuGen = null, // Todo 552 srcData = Seq( 553 Seq(IntData()), 554 ), 555 piped = true, 556 latency = CertainLatency(0), 557 ) 558 559 val VialuCfg = FuConfig ( 560 name = "vialuFix", 561 fuType = FuType.vialuF, 562 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 563 srcData = Seq( 564 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 565 ), 566 piped = true, 567 writeVecRf = true, 568 writeVxsat = true, 569 needSrcVxrm = true, 570 latency = CertainLatency(1), 571 vconfigWakeUp = true, 572 maskWakeUp = true, 573 dataBits = 128, 574 exceptionOut = Seq(illegalInstr), 575 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 576 ) 577 578 val VimacCfg = FuConfig ( 579 name = "vimac", 580 fuType = FuType.vimac, 581 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 582 srcData = Seq( 583 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 584 ), 585 piped = true, 586 writeVecRf = true, 587 writeVxsat = true, 588 needSrcVxrm = true, 589 latency = CertainLatency(2), 590 vconfigWakeUp = true, 591 maskWakeUp = true, 592 dataBits = 128, 593 exceptionOut = Seq(illegalInstr), 594 ) 595 596 val VidivCfg = FuConfig ( 597 name = "vidiv", 598 fuType = FuType.vidiv, 599 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 600 srcData = Seq( 601 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 602 ), 603 piped = false, 604 writeVecRf = true, 605 latency = UncertainLatency(), 606 vconfigWakeUp = true, 607 maskWakeUp = true, 608 dataBits = 128, 609 exceptionOut = Seq(illegalInstr), 610 ) 611 612 val VppuCfg = FuConfig ( 613 name = "vppu", 614 fuType = FuType.vppu, 615 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 616 srcData = Seq( 617 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 618 ), 619 piped = true, 620 writeVecRf = true, 621 latency = CertainLatency(2), 622 vconfigWakeUp = true, 623 maskWakeUp = true, 624 dataBits = 128, 625 exceptionOut = Seq(illegalInstr), 626 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 627 ) 628 629 val VipuCfg: FuConfig = FuConfig ( 630 name = "vipu", 631 fuType = FuType.vipu, 632 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 633 srcData = Seq( 634 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 635 ), 636 piped = true, 637 writeIntRf = true, 638 writeVecRf = true, 639 latency = CertainLatency(2), 640 vconfigWakeUp = true, 641 maskWakeUp = true, 642 dataBits = 128, 643 exceptionOut = Seq(illegalInstr), 644 ) 645 646 val VfaluCfg = FuConfig ( 647 name = "vfalu", 648 fuType = FuType.vfalu, 649 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 650 srcData = Seq( 651 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 652 ), 653 piped = true, 654 writeVecRf = true, 655 writeFpRf = true, 656 writeIntRf = true, 657 writeFflags = true, 658 latency = CertainLatency(1), 659 vconfigWakeUp = true, 660 maskWakeUp = true, 661 dataBits = 128, 662 exceptionOut = Seq(illegalInstr), 663 needSrcFrm = true, 664 ) 665 666 val VfmaCfg = FuConfig ( 667 name = "vfma", 668 fuType = FuType.vfma, 669 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 670 srcData = Seq( 671 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 672 ), 673 piped = true, 674 writeVecRf = true, 675 writeFpRf = true, 676 writeFflags = true, 677 latency = CertainLatency(3), 678 vconfigWakeUp = true, 679 maskWakeUp = true, 680 dataBits = 128, 681 exceptionOut = Seq(illegalInstr), 682 needSrcFrm = true, 683 ) 684 685 val VfdivCfg = FuConfig( 686 name = "vfdiv", 687 fuType = FuType.vfdiv, 688 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 689 srcData = Seq( 690 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 691 ), 692 piped = false, 693 writeVecRf = true, 694 writeFpRf = true, 695 writeFflags = true, 696 latency = UncertainLatency(), 697 vconfigWakeUp = true, 698 maskWakeUp = true, 699 dataBits = 128, 700 exceptionOut = Seq(illegalInstr), 701 needSrcFrm = true, 702 ) 703 704 val VfcvtCfg = FuConfig( 705 name = "vfcvt", 706 fuType = FuType.vfcvt, 707 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 708 srcData = Seq( 709 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 710 ), 711 piped = true, 712 writeVecRf = true, 713 writeFpRf = true, 714 writeIntRf = true, 715 writeFflags = true, 716 latency = CertainLatency(2), 717 vconfigWakeUp = true, 718 maskWakeUp = true, 719 dataBits = 128, 720 exceptionOut = Seq(illegalInstr), 721 needSrcFrm = true, 722 ) 723 724 725 val VlduCfg: FuConfig = FuConfig ( 726 name = "vldu", 727 fuType = FuType.vldu, 728 fuGen = null, 729 srcData = Seq( 730 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 731 ), 732 piped = false, // Todo: check it 733 writeVecRf = true, 734 latency = UncertainLatency(), 735 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 736 flushPipe = true, 737 replayInst = true, 738 hasLoadError = true, 739 vconfigWakeUp = true, 740 maskWakeUp = true, 741 dataBits = 128, 742 ) 743 744 val VstuCfg: FuConfig = FuConfig ( 745 name = "vstu", 746 fuType = FuType.vstu, 747 fuGen = null, 748 srcData = Seq( 749 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 750 ), 751 piped = false, 752 writeVecRf = false, 753 latency = UncertainLatency(), 754 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 755 flushPipe = true, 756 replayInst = true, 757 hasLoadError = true, 758 vconfigWakeUp = true, 759 maskWakeUp = true, 760 dataBits = 128, 761 ) 762 763 def allConfigs = Seq( 764 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 765 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 766 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 767 ) 768 769 def VecArithFuConfigs = Seq( 770 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 771 ) 772} 773 774