xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala (revision a9ecfa67572f9dc8d32a66b8924cfc8e21bbda0c) 
1package xiangshan.backend.exu
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7
8import xiangshan.backend.FenceOpType
9
10class FenceToSbuffer extends XSBundle {
11  val flushSb = Output(Bool())
12  val sbIsEmpty = Input(Bool())
13}
14
15class FenceExeUnit extends Exu(Exu.fenceExeUnitCfg) {
16
17  val sfence = IO(Output(new SfenceBundle))
18  val fencei = IO(Output(Bool()))
19  val toSbuffer = IO(new FenceToSbuffer)
20
21  val (valid, src1, src2, uop, func, lsrc1, lsrc2) =
22    (io.in.valid, io.in.bits.src1, io.in.bits.src2, io.in.bits.uop, io.in.bits.uop.ctrl.fuOpType, io.in.bits.uop.ctrl.lsrc1, io.in.bits.uop.ctrl.lsrc2)
23
24  val s_sb :: s_tlb :: s_icache :: s_none :: Nil = Enum(4)
25  val state = RegInit(s_sb)
26
27  val sbuffer = toSbuffer.flushSb
28  val sbEmpty = toSbuffer.sbIsEmpty
29
30  // NOTE: icache & tlb & sbuffer must receive flush signal at any time
31  sbuffer      := valid && state === s_sb && !sbEmpty
32  fencei       := (state === s_icache && sbEmpty) || (state === s_sb && valid && sbEmpty && func === FenceOpType.fencei)
33  sfence.valid := (state === s_tlb && sbEmpty) || (state === s_sb && valid && sbEmpty && func === FenceOpType.sfence)
34  sfence.bits.rs1  := Mux(state === s_sb, lsrc1 === 0.U, RegEnable(lsrc1 === 0.U, io.in.fire()))
35  sfence.bits.rs2  := Mux(state === s_sb, lsrc2 === 0.U, RegEnable(lsrc2 === 0.U, io.in.fire()))
36  sfence.bits.addr := Mux(state === s_sb, src1,          RegEnable(src1, io.in.fire()))
37
38  when (state === s_sb && valid && func === FenceOpType.fencei && !sbEmpty) { state := s_icache }
39  when (state === s_sb && valid && func === FenceOpType.sfence && !sbEmpty) { state := s_tlb }
40  when (state === s_sb && valid && func === FenceOpType.fence  && !sbEmpty) { state := s_none }
41  when (state =/= s_sb && sbEmpty) { state := s_sb }
42
43  assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen))
44  io.in.ready := state === s_sb
45  io.out.valid := (state =/= s_sb && sbEmpty) || (state === s_sb && sbEmpty && valid)
46  io.out.bits.data := DontCare
47  io.out.bits.uop := Mux(state === s_sb, uop, RegEnable(uop, io.in.fire()))
48  io.out.bits.redirect <> DontCare
49  io.out.bits.redirectValid := false.B
50  io.out.bits.debug <> DontCare
51  io.csrOnly <> DontCare
52
53  assert(!(valid || state =/= s_sb) || io.out.ready) // NOTE: fence instr must be the first(only one) instr, so io.out.ready must be true
54
55  XSDebug(valid || state=/=s_sb || io.out.valid, p"In(${io.in.valid} ${io.in.ready}) Out(${io.out.valid} ${io.out.ready}) state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InroqIdx:${io.in.bits.uop.roqIdx} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutroqIdx:${io.out.bits.uop.roqIdx}\n")
56}
57