xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala (revision 10b9babd805e02359c6fee797c66e99cd4a296ec) 
1package xiangshan.backend.fu
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import xiangshan.backend.FenceOpType
8
9class FenceToSbuffer extends XSBundle {
10  val flushSb = Output(Bool())
11  val sbIsEmpty = Input(Bool())
12}
13
14class Fence extends FunctionUnit(FuConfig(
15  FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false
16)){
17
18  val sfence = IO(Output(new SfenceBundle))
19  val fencei = IO(Output(Bool()))
20  val toSbuffer = IO(new FenceToSbuffer)
21
22  val (valid, src1, uop, func, lsrc1, lsrc2) = (
23    io.in.valid,
24    io.in.bits.src(0),
25    io.in.bits.uop,
26    io.in.bits.uop.ctrl.fuOpType,
27    io.in.bits.uop.ctrl.lsrc1,
28    io.in.bits.uop.ctrl.lsrc2
29  )
30
31  val s_sb :: s_tlb :: s_icache :: s_none :: Nil = Enum(4)
32  val state = RegInit(s_sb)
33
34  val sbuffer = toSbuffer.flushSb
35  val sbEmpty = toSbuffer.sbIsEmpty
36
37  // NOTE: icache & tlb & sbuffer must receive flush signal at any time
38  sbuffer      := valid && state === s_sb && !sbEmpty
39  fencei       := (state === s_icache && sbEmpty) || (state === s_sb && valid && sbEmpty && func === FenceOpType.fencei)
40  sfence.valid := (state === s_tlb && sbEmpty) || (state === s_sb && valid && sbEmpty && func === FenceOpType.sfence)
41  sfence.bits.rs1  := Mux(state === s_sb, lsrc1 === 0.U, RegEnable(lsrc1 === 0.U, io.in.fire()))
42  sfence.bits.rs2  := Mux(state === s_sb, lsrc2 === 0.U, RegEnable(lsrc2 === 0.U, io.in.fire()))
43  sfence.bits.addr := Mux(state === s_sb, src1,          RegEnable(src1, io.in.fire()))
44
45  when (state === s_sb && valid && func === FenceOpType.fencei && !sbEmpty) { state := s_icache }
46  when (state === s_sb && valid && func === FenceOpType.sfence && !sbEmpty) { state := s_tlb }
47  when (state === s_sb && valid && func === FenceOpType.fence  && !sbEmpty) { state := s_none }
48  when (state =/= s_sb && sbEmpty) { state := s_sb }
49
50  assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen))
51  io.in.ready := state === s_sb
52  io.out.valid := (state =/= s_sb && sbEmpty) || (state === s_sb && sbEmpty && valid)
53  io.out.bits.data := DontCare
54  io.out.bits.uop := Mux(state === s_sb, uop, RegEnable(uop, io.in.fire()))
55
56  assert(!(valid || state =/= s_sb) || io.out.ready) // NOTE: fence instr must be the first(only one) instr, so io.out.ready must be true
57
58  XSDebug(valid || state=/=s_sb || io.out.valid, p"In(${io.in.valid} ${io.in.ready}) Out(${io.out.valid} ${io.out.ready}) state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InroqIdx:${io.in.bits.uop.roqIdx} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutroqIdx:${io.out.bits.uop.roqIdx}\n")
59}
60