xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala (revision b086c6da80b5e7e939f9ce8dde0b13f881c26a65) 
1package xiangshan.backend.fu
2
3import chisel3._
4import chisel3.util._
5import utils.{LookupTree, LookupTreeDefault, ParallelMux, SignExt, XSDebug, ZeroExt}
6import xiangshan._
7import xiangshan.backend.ALUOpType
8
9class Alu extends FunctionUnit with HasRedirectOut {
10
11  val (src1, src2, offset, func, pc, uop) = (
12    io.in.bits.src(0),
13    io.in.bits.src(1),
14    io.in.bits.uop.ctrl.imm,
15    io.in.bits.uop.ctrl.fuOpType,
16    SignExt(io.in.bits.uop.cf.pc, AddrBits),
17    io.in.bits.uop
18  )
19
20  val valid = io.in.valid
21
22  val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw)
23  val addRes = src1 +& src2
24  val subRes = (src1 +& (~src2).asUInt()) + 1.U
25  val xorRes = src1 ^ src2
26  val sltu = !subRes(XLEN)
27  val slt = xorRes(XLEN-1) ^ sltu
28
29  val shsrc1 = LookupTreeDefault(func, src1, List(
30    ALUOpType.srlw -> ZeroExt(src1(31,0), 64),
31    ALUOpType.sraw -> SignExt(src1(31,0), 64)
32  ))
33  val shamt = Mux(ALUOpType.isWordOp(func), src2(4, 0), src2(5, 0))
34
35  val miscRes = ParallelMux(List(
36    ALUOpType.sll  -> (shsrc1 << shamt)(XLEN-1, 0),
37    ALUOpType.slt  -> ZeroExt(slt, XLEN),
38    ALUOpType.sltu -> ZeroExt(sltu, XLEN),
39    ALUOpType.xor  -> xorRes,
40    ALUOpType.srl  -> (shsrc1 >> shamt),
41    ALUOpType.or   -> (src1 | src2),
42    ALUOpType.and  -> (src1 & src2),
43    ALUOpType.sra  -> (shsrc1.asSInt >> shamt).asUInt
44  ).map(x => (x._1 === func(3, 0), x._2)))
45
46  val res = Mux(ALUOpType.isAddSub(func),
47    Mux(isAdderSub, subRes, addRes),
48    miscRes
49  )
50
51  val aluRes = Mux(ALUOpType.isWordOp(func), SignExt(res(31,0), 64), res)
52
53  val branchOpTable = List(
54    ALUOpType.getBranchType(ALUOpType.beq)  -> !xorRes.orR,
55    ALUOpType.getBranchType(ALUOpType.blt)  -> slt,
56    ALUOpType.getBranchType(ALUOpType.bltu) -> sltu
57  )
58
59  val isBranch = ALUOpType.isBranch(func)
60  val isRVC = uop.cf.brUpdate.pd.isRVC
61  val taken = LookupTree(ALUOpType.getBranchType(func), branchOpTable) ^ ALUOpType.isBranchInvert(func)
62  val target = (pc + offset)(VAddrBits-1,0)
63  val snpc = Mux(isRVC, pc + 2.U, pc + 4.U)
64
65  redirectOutValid := io.out.valid && isBranch
66  redirectOut.pc := uop.cf.pc
67  redirectOut.target := Mux(!taken && isBranch, snpc, target)
68  redirectOut.brTag := uop.brTag
69  redirectOut.level := RedirectLevel.flushAfter
70  redirectOut.interrupt := DontCare
71  redirectOut.roqIdx := uop.roqIdx
72
73  brUpdate := uop.cf.brUpdate
74  // override brUpdate
75  brUpdate.pc := uop.cf.pc
76  brUpdate.target := Mux(!taken && isBranch, snpc, target)
77  brUpdate.brTarget := target
78  brUpdate.taken := isBranch && taken
79  brUpdate.brTag := uop.brTag
80
81  io.in.ready := io.out.ready
82  io.out.valid := valid
83  io.out.bits.uop <> io.in.bits.uop
84  io.out.bits.data := aluRes
85}
86