1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.dispatch 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import xiangshan.ExceptionNO._ 24import xiangshan._ 25import xiangshan.backend.MemCoreTopDownIO 26import xiangshan.backend.rob.{RobDispatchTopDownIO, RobEnqIO} 27import xiangshan.mem.mdp._ 28import xiangshan.mem.{HasVLSUParameters, _} 29import xiangshan.backend.Bundles.{DecodedInst, DynInst, ExuVec, IssueQueueIQWakeUpBundle} 30import xiangshan.backend.fu.{FuConfig, FuType} 31import xiangshan.backend.rename.BusyTable 32import chisel3.util.experimental.decode._ 33import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 34import xiangshan.backend.fu.{FuConfig, FuType} 35import xiangshan.backend.rename.BusyTableReadIO 36import xiangshan.backend.datapath.DataConfig._ 37import xiangshan.backend.datapath.WbConfig._ 38import xiangshan.backend.datapath.DataSource 39import xiangshan.backend.datapath.WbConfig.VfWB 40import xiangshan.backend.fu.FuType.FuTypeOrR 41import xiangshan.backend.dispatch.Dispatch2IqFpImp 42import xiangshan.backend.regcache.{RCTagTableReadPort, RegCacheTagTable} 43 44 45// TODO delete trigger message from frontend to iq 46class NewDispatch(implicit p: Parameters) extends XSModule with HasPerfEvents with HasVLSUParameters { 47 // std IQ donot need dispatch, only copy sta IQ, but need sta IQ's ready && std IQ's ready 48 val allIssueParams = backendParams.allIssueParams.filter(_.StdCnt == 0) 49 val allExuParams = allIssueParams.map(_.exuBlockParams).flatten 50 val allFuConfigs = allExuParams.map(_.fuConfigs).flatten.toSet.toSeq 51 val sortedFuConfigs = allFuConfigs.sortBy(_.fuType.id) 52 println(s"[NewDispatch] ${allExuParams.map(_.name)}") 53 println(s"[NewDispatch] ${allFuConfigs.map(_.name)}") 54 println(s"[NewDispatch] ${allFuConfigs.map(_.fuType.id)}") 55 println(s"[NewDispatch] ${sortedFuConfigs.map(_.name)}") 56 println(s"[NewDispatch] ${sortedFuConfigs.map(_.fuType.id)}") 57 val fuConfigsInIssueParams = allIssueParams.map(_.allExuParams.map(_.fuConfigs).flatten.toSet.toSeq) 58 val fuMapIQIdx = sortedFuConfigs.map( fu => { 59 val fuInIQIdx = fuConfigsInIssueParams.zipWithIndex.filter { case (f, i) => f.contains(fu) }.map(_._2) 60 (fu -> fuInIQIdx) 61 } 62 ) 63 fuMapIQIdx.map { case (fu, iqidx) => 64 println(s"[NewDispatch] ${fu.name} $iqidx") 65 } 66 val sameIQIdxFus = fuMapIQIdx.map{ case (fu, iqidx) => 67 fuMapIQIdx.filter(_._2 == iqidx).map(_._1) -> iqidx 68 }.toSet.toSeq 69 val needMultiIQ = sameIQIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size > 1) 70 val needSingleIQ = sameIQIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size == 1) 71 needMultiIQ.map { case (fus, iqidx) => 72 println(s"[NewDispatch] needMultiIQ: ${fus.map(_.name)} $iqidx") 73 } 74 needSingleIQ.map { case (fus, iqidx) => 75 println(s"[NewDispatch] needSingleIQ: ${fus.map(_.name)} $iqidx") 76 } 77 val fuConfigsInExuParams = allExuParams.map(_.fuConfigs) 78 val fuMapExuIdx = sortedFuConfigs.map { case fu => { 79 val fuInExuIdx = fuConfigsInExuParams.zipWithIndex.filter { case (f, i) => f.contains(fu) }.map(_._2) 80 (fu -> fuInExuIdx) 81 } 82 } 83 val sameExuIdxFus = fuMapExuIdx.map { case (fu, exuidx) => 84 fuMapExuIdx.filter(_._2 == exuidx).map(_._1) -> exuidx 85 }.toSet.toSeq 86 val needMultiExu = sameExuIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size > 1).filter{ x => 87 x._1.map(y => fuMapIQIdx.filter(_._1 == y).head._2.size > 1).reduce(_ && _) 88 } 89 90 val exuNum = allExuParams.size 91 val maxIQSize = allIssueParams.map(_.numEntries).max 92 val IQEnqSum = allIssueParams.map(_.numEnq).sum 93 94 val io = IO(new Bundle { 95 // from rename 96 val renameIn = Vec(RenameWidth, Flipped(ValidIO(new DecodedInst))) 97 val fromRename = Vec(RenameWidth, Flipped(DecoupledIO(new DynInst))) 98 val toRenameAllFire = Output(Bool()) 99 // enq Rob 100 val enqRob = Flipped(new RobEnqIO) 101 // IssueQueues 102 val IQValidNumVec = Vec(exuNum, Input(UInt(maxIQSize.U.getWidth.W))) 103 val toIssueQueues = Vec(IQEnqSum, DecoupledIO(new DynInst)) 104 // to busyTable 105 // set preg state to ready (write back regfile) 106 val wbPregsInt = Vec(backendParams.numPregWb(IntData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 107 val wbPregsFp = Vec(backendParams.numPregWb(FpData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 108 val wbPregsVec = Vec(backendParams.numPregWb(VecData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 109 val wbPregsV0 = Vec(backendParams.numPregWb(V0Data()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 110 val wbPregsVl = Vec(backendParams.numPregWb(VlData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 111 val wakeUpAll = new Bundle { 112 val wakeUpInt: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.intSchdParams.get.genIQWakeUpOutValidBundle) 113 val wakeUpFp: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.fpSchdParams.get.genIQWakeUpOutValidBundle) 114 val wakeUpVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.vfSchdParams.get.genIQWakeUpOutValidBundle) 115 val wakeUpMem: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.memSchdParams.get.genIQWakeUpOutValidBundle) 116 } 117 val og0Cancel = Input(ExuVec()) 118 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 119 // from MemBlock 120 val fromMem = new Bundle { 121 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 122 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 123 val lqDeqPtr = Input(new LqPtr) 124 val sqDeqPtr = Input(new SqPtr) 125 // from lsq 126 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 127 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 128 } 129 //toMem 130 val toMem = new Bundle { 131 val lsqEnqIO = Flipped(new LsqEnqIO) 132 } 133 // redirect 134 val redirect = Flipped(ValidIO(new Redirect)) 135 // singleStep 136 val singleStep = Input(Bool()) 137 // lfst 138 val lfst = new DispatchLFSTIO 139 140 // perf only 141 val robHead = Input(new DynInst) 142 val stallReason = Flipped(new StallReasonIO(RenameWidth)) 143 val lqCanAccept = Input(Bool()) 144 val sqCanAccept = Input(Bool()) 145 val robHeadNotReady = Input(Bool()) 146 val robFull = Input(Bool()) 147 val debugTopDown = new Bundle { 148 val fromRob = Flipped(new RobDispatchTopDownIO) 149 val fromCore = new CoreDispatchTopDownIO 150 } 151 }) 152 // Deq for std's IQ is not assigned in Dispatch2Iq, so add one more src for it. 153 val issueBlockParams = backendParams.allIssueParams 154 val renameIn = io.renameIn 155 val fromRename = io.fromRename 156 io.toRenameAllFire := io.fromRename.map(x => !x.valid || x.fire).reduce(_ && _) 157 val fromRenameUpdate = Wire(Vec(RenameWidth, Flipped(ValidIO(new DynInst)))) 158 fromRenameUpdate := fromRename 159 val renameWidth = io.fromRename.size 160 val issueQueueCount = io.IQValidNumVec 161 val issueQueueNum = allIssueParams.size 162 // int fp vec v0 vl 163 val numRegType = 5 164 val idxRegTypeInt = allFuConfigs.map(x => { 165 x.srcData.map(xx => { 166 xx.zipWithIndex.filter(y => IntRegSrcDataSet.contains(y._1)).map(_._2) 167 }).flatten 168 }).flatten.toSet.toSeq.sorted 169 val idxRegTypeFp = allFuConfigs.map(x => { 170 x.srcData.map(xx => { 171 xx.zipWithIndex.filter(y => FpRegSrcDataSet.contains(y._1)).map(_._2) 172 }).flatten 173 }).flatten.toSet.toSeq.sorted 174 val idxRegTypeVec = allFuConfigs.map(x => { 175 x.srcData.map(xx => { 176 xx.zipWithIndex.filter(y => VecRegSrcDataSet.contains(y._1)).map(_._2) 177 }).flatten 178 }).flatten.toSet.toSeq.sorted 179 val idxRegTypeV0 = allFuConfigs.map(x => { 180 x.srcData.map(xx => { 181 xx.zipWithIndex.filter(y => V0RegSrcDataSet.contains(y._1)).map(_._2) 182 }).flatten 183 }).flatten.toSet.toSeq.sorted 184 val idxRegTypeVl = allFuConfigs.map(x => { 185 x.srcData.map(xx => { 186 xx.zipWithIndex.filter(y => VlRegSrcDataSet.contains(y._1)).map(_._2) 187 }).flatten 188 }).flatten.toSet.toSeq.sorted 189 println(s"[NewDispatch] idxRegTypeInt: $idxRegTypeInt") 190 println(s"[NewDispatch] idxRegTypeFp: $idxRegTypeFp") 191 println(s"[NewDispatch] idxRegTypeVec: $idxRegTypeVec") 192 println(s"[NewDispatch] idxRegTypeV0: $idxRegTypeV0") 193 println(s"[NewDispatch] idxRegTypeVl: $idxRegTypeVl") 194 val numRegSrc: Int = issueBlockParams.map(_.exuBlockParams.map( 195 x => if (x.hasStdFu) x.numRegSrc + 1 else x.numRegSrc 196 ).max).max 197 198 val numRegSrcInt: Int = issueBlockParams.map(_.exuBlockParams.map( 199 x => if (x.hasStdFu) x.numIntSrc + 1 else x.numIntSrc 200 ).max).max 201 val numRegSrcFp: Int = issueBlockParams.map(_.exuBlockParams.map( 202 x => if (x.hasStdFu) x.numFpSrc + 1 else x.numFpSrc 203 ).max).max 204 val numRegSrcVf: Int = issueBlockParams.map(_.exuBlockParams.map( 205 x => x.numVecSrc 206 ).max).max 207 val numRegSrcV0: Int = issueBlockParams.map(_.exuBlockParams.map( 208 x => x.numV0Src 209 ).max).max 210 val numRegSrcVl: Int = issueBlockParams.map(_.exuBlockParams.map( 211 x => x.numVlSrc 212 ).max).max 213 214 println(s"[Dispatch2Iq] numRegSrc: ${numRegSrc}, numRegSrcInt: ${numRegSrcInt}, numRegSrcFp: ${numRegSrcFp}, " + 215 s"numRegSrcVf: ${numRegSrcVf}, numRegSrcV0: ${numRegSrcV0}, numRegSrcVl: ${numRegSrcVl}") 216 217 // RegCacheTagTable Module 218 val rcTagTable = Module(new RegCacheTagTable(numRegSrcInt * renameWidth)) 219 // BusyTable Modules 220 val intBusyTable = Module(new BusyTable(numRegSrcInt * renameWidth, backendParams.numPregWb(IntData()), IntPhyRegs, IntWB())) 221 val fpBusyTable = Module(new BusyTable(numRegSrcFp * renameWidth, backendParams.numPregWb(FpData()), FpPhyRegs, FpWB())) 222 val vecBusyTable = Module(new BusyTable(numRegSrcVf * renameWidth, backendParams.numPregWb(VecData()), VfPhyRegs, VfWB())) 223 val v0BusyTable = Module(new BusyTable(numRegSrcV0 * renameWidth, backendParams.numPregWb(V0Data()), V0PhyRegs, V0WB())) 224 val vlBusyTable = Module(new BusyTable(numRegSrcVl * renameWidth, backendParams.numPregWb(VlData()), VlPhyRegs, VlWB())) 225 val busyTables = Seq(intBusyTable, fpBusyTable, vecBusyTable, v0BusyTable, vlBusyTable) 226 val wbPregs = Seq(io.wbPregsInt, io.wbPregsFp, io.wbPregsVec, io.wbPregsV0, io.wbPregsVl) 227 val idxRegType = Seq(idxRegTypeInt, idxRegTypeFp, idxRegTypeVec, idxRegTypeV0, idxRegTypeVl) 228 val allocPregsValid = Wire(Vec(busyTables.size, Vec(RenameWidth, Bool()))) 229 allocPregsValid(0) := VecInit(fromRename.map(x => x.valid && x.bits.rfWen && !x.bits.eliminatedMove)) 230 allocPregsValid(1) := VecInit(fromRename.map(x => x.valid && x.bits.fpWen)) 231 allocPregsValid(2) := VecInit(fromRename.map(x => x.valid && x.bits.vecWen)) 232 allocPregsValid(3) := VecInit(fromRename.map(x => x.valid && x.bits.v0Wen)) 233 allocPregsValid(4) := VecInit(fromRename.map(x => x.valid && x.bits.vlWen)) 234 val allocPregs = Wire(Vec(busyTables.size, Vec(RenameWidth, ValidIO(UInt(PhyRegIdxWidth.W))))) 235 allocPregs.zip(allocPregsValid).map(x =>{ 236 x._1.zip(x._2).zipWithIndex.map{case ((sink, source), i) => { 237 sink.valid := source 238 sink.bits := fromRename(i).bits.pdest 239 }} 240 }) 241 val wakeUp = io.wakeUpAll.wakeUpInt ++ io.wakeUpAll.wakeUpFp ++ io.wakeUpAll.wakeUpVec ++ io.wakeUpAll.wakeUpMem 242 busyTables.zip(wbPregs).zip(allocPregs).map{ case ((b, w), a) => { 243 b.io.wakeUpInt := io.wakeUpAll.wakeUpInt 244 b.io.wakeUpFp := io.wakeUpAll.wakeUpFp 245 b.io.wakeUpVec := io.wakeUpAll.wakeUpVec 246 b.io.wakeUpMem := io.wakeUpAll.wakeUpMem 247 b.io.og0Cancel := io.og0Cancel 248 b.io.ldCancel := io.ldCancel 249 b.io.wbPregs := w 250 b.io.allocPregs := a 251 }} 252 rcTagTable.io.allocPregs.zip(allocPregs(0)).map(x => x._1 := x._2) 253 rcTagTable.io.wakeupFromIQ := io.wakeUpAll.wakeUpInt ++ io.wakeUpAll.wakeUpMem 254 rcTagTable.io.og0Cancel := io.og0Cancel 255 rcTagTable.io.ldCancel := io.ldCancel 256 busyTables.zip(idxRegType).zipWithIndex.map { case ((b, idxseq), i) => { 257 val readAddr = VecInit(fromRename.map(x => x.bits.psrc.zipWithIndex.filter(xx => idxseq.contains(xx._2)).map(_._1)).flatten) 258 val readValid = VecInit(fromRename.map(x => x.bits.psrc.zipWithIndex.filter(xx => idxseq.contains(xx._2)).map(y => x.valid && SrcType.isXp(x.bits.srcType(y._2)))).flatten) 259 b.io.read.map(_.req).zip(readAddr).map(x => x._1 := x._2) 260 // only int src need srcLoadDependency, src0 src1 261 if (i == 0) { 262 val srcLoadDependencyUpdate = fromRenameUpdate.map(x => x.bits.srcLoadDependency.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 263 val srcType = fromRenameUpdate.map(x => x.bits.srcType.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 264 // for std, int src need srcLoadDependency, fp src donot need srcLoadDependency 265 srcLoadDependencyUpdate.lazyZip(b.io.read.map(_.loadDependency)).lazyZip(srcType).map{ case (sink, source, srctype) => 266 sink := Mux(SrcType.isXp(srctype), source, 0.U.asTypeOf(sink)) 267 } 268 // only int src need rcTag 269 val rcTagUpdate = fromRenameUpdate.map(x => x.bits.regCacheIdx.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 270 rcTagUpdate.zip(rcTagTable.io.readPorts.map(_.addr)).map(x => x._1 := x._2) 271 val useRegCacheUpdate = fromRenameUpdate.map(x => x.bits.useRegCache.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 272 useRegCacheUpdate.zip(rcTagTable.io.readPorts.map(_.valid)).map(x => x._1 := x._2) 273 rcTagTable.io.readPorts.map(_.ren).zip(readValid).map(x => x._1 := x._2) 274 rcTagTable.io.readPorts.map(_.tag).zip(readAddr).map(x => x._1 := x._2) 275 } 276 }} 277 val allSrcState = Wire(Vec(renameWidth, Vec(numRegSrc, Vec(numRegType, Bool())))) 278 for (i <- 0 until renameWidth){ 279 for (j <- 0 until numRegSrc){ 280 for (k <- 0 until numRegType){ 281 if (!idxRegType(k).contains(j)) { 282 allSrcState(i)(j)(k) := false.B 283 } 284 else { 285 val readidx = i * idxRegType(k).size + idxRegType(k).indexOf(j) 286 val readEn = k match { 287 case 0 => SrcType.isXp(fromRename(i).bits.srcType(j)) 288 case 1 => SrcType.isFp(fromRename(i).bits.srcType(j)) 289 case 2 => SrcType.isVp(fromRename(i).bits.srcType(j)) 290 case 3 => SrcType.isV0(fromRename(i).bits.srcType(j)) 291 case 4 => true.B 292 } 293 allSrcState(i)(j)(k) := readEn && busyTables(k).io.read(readidx).resp || SrcType.isImm(fromRename(i).bits.srcType(j)) 294 } 295 } 296 } 297 } 298 299 // Singlestep should only commit one machine instruction after dret, and then hart enter debugMode according to singlestep exception. 300 val s_holdRobidx :: s_updateRobidx :: Nil = Enum(2) 301 val singleStepState = RegInit(s_updateRobidx) 302 303 val robidxStepNext = WireInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 304 val robidxStepReg = RegInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 305 val robidxCanCommitStepping = WireInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 306 307 when(!io.singleStep) { 308 singleStepState := s_updateRobidx 309 }.elsewhen(io.singleStep && fromRename(0).fire && io.enqRob.req(0).valid) { 310 singleStepState := s_holdRobidx 311 robidxStepNext := fromRename(0).bits.robIdx 312 } 313 314 when(singleStepState === s_updateRobidx) { 315 robidxStepReg := robidxStepNext 316 robidxCanCommitStepping := robidxStepNext 317 }.elsewhen(singleStepState === s_holdRobidx) { 318 robidxStepReg := robidxStepReg 319 robidxCanCommitStepping := robidxStepReg 320 } 321 322 val minIQSelAll = Wire(Vec(needMultiExu.size, Vec(renameWidth, Vec(issueQueueNum, Bool())))) 323 needMultiExu.zipWithIndex.map{ case ((fus, exuidx), needMultiExuidx) => { 324 val suffix = fus.map(_.name).mkString("_") 325 val iqNum = exuidx.size 326 val iqidx = allIssueParams.map(_.exuBlockParams.map(_.fuConfigs).flatten.toSet.toSeq).zipWithIndex.filter{x => fus.toSet.subsetOf(x._1.toSet)}.map(_._2) 327 println(s"[NewDispatch] ${fus.map(_.name)};iqidx:$iqidx;exuIdx:$exuidx") 328 val compareMatrix = Wire(Vec(iqNum, Vec(iqNum, Bool()))).suggestName(s"compareMatrix_$suffix") 329 for (i <- 0 until iqNum) { 330 for (j <- 0 until iqNum) { 331 if (i == j) compareMatrix(i)(j) := false.B 332 else if (i < j) compareMatrix(i)(j) := issueQueueCount(exuidx(i)) < issueQueueCount(exuidx(j)) 333 else compareMatrix(i)(j) := !compareMatrix(j)(i) 334 } 335 } 336 val IQSort = Reg(Vec(iqNum, Vec(iqNum, Bool()))).suggestName(s"IQSort_$suffix}") 337 for (i <- 0 until iqNum){ 338 // i = 0 minimum iq, i = iqNum - 1 -> maximum iq 339 IQSort(i) := compareMatrix.map(x => PopCount(x) === (iqNum - 1 - i).U) 340 } 341 val minIQSel = Wire(Vec(renameWidth, Vec(issueQueueNum, Bool()))).suggestName(s"minIQSel_$suffix") 342 for (i <- 0 until renameWidth){ 343 val minIQSel_ith = IQSort(i % iqNum) 344 println(s"minIQSel_${i}th_$suffix = IQSort(${i % iqNum})") 345 for (j <- 0 until issueQueueNum){ 346 minIQSel(i)(j) := false.B 347 if (iqidx.contains(j)){ 348 minIQSel(i)(j) := minIQSel_ith(iqidx.indexOf(j)) 349 println(s"minIQSel_${suffix}_${i}_${j} = minIQSel_ith(iqidx.indexOf(${j}))") 350 } 351 } 352 } 353 minIQSelAll(needMultiExuidx) := minIQSel 354 if (backendParams.debugEn){ 355 dontTouch(compareMatrix) 356 dontTouch(IQSort) 357 dontTouch(minIQSel) 358 } 359 } 360 } 361 val fuConfigSeq = needMultiExu.map(_._1) 362 val fuTypeOH = Wire(Vec(renameWidth, Vec(needMultiExu.size, Bool()))) 363 fuTypeOH.zip(renameIn).map{ case(oh, in) => { 364 oh := fuConfigSeq.map(x => x.map(xx => in.bits.fuType(xx.fuType.id)).reduce(_ || _) && in.valid) 365 } 366 } 367 // not count itself 368 val popFuTypeOH = Wire(Vec(renameWidth, Vec(needMultiExu.size, UInt((renameWidth-1).U.getWidth.W)))) 369 popFuTypeOH.zipWithIndex.map{ case (pop, idx) => { 370 if (idx == 0){ 371 pop := 0.U.asTypeOf(pop) 372 } 373 else { 374 pop.zipWithIndex.map{ case (p, i) => { 375 p := PopCount(fuTypeOH.take(idx).map(x => x(i))) 376 } 377 } 378 } 379 }} 380 val uopSelIQ = Reg(Vec(renameWidth, Vec(issueQueueNum, Bool()))) 381 val fuTypeOHSingle = Wire(Vec(renameWidth, Vec(needSingleIQ.size, Bool()))) 382 fuTypeOHSingle.zip(renameIn).map{ case (oh, in) => { 383 oh := needSingleIQ.map(_._1).map(x => x.map(xx => in.valid && in.bits.fuType(xx.fuType.id)).reduce(_ || _)) 384 }} 385 val uopSelIQSingle = Wire(Vec(needSingleIQ.size, Vec(issueQueueNum, Bool()))) 386 uopSelIQSingle := VecInit(needSingleIQ.map(_._2).flatten.map(x => VecInit((1.U(issueQueueNum.W) << x)(issueQueueNum-1, 0).asBools))) 387 uopSelIQ.zipWithIndex.map{ case (u, i) => { 388 when(io.toRenameAllFire){ 389 u := Mux(renameIn(i).valid, 390 Mux(fuTypeOH(i).asUInt.orR, 391 Mux1H(fuTypeOH(i), minIQSelAll)(Mux1H(fuTypeOH(i), popFuTypeOH(i))), 392 Mux1H(fuTypeOHSingle(i), uopSelIQSingle)), 393 0.U.asTypeOf(u) 394 ) 395 }.elsewhen(io.fromRename(i).fire){ 396 u := 0.U.asTypeOf(u) 397 } 398 }} 399 val uopSelIQMatrix = Wire(Vec(renameWidth, Vec(issueQueueNum, UInt(renameWidth.U.getWidth.W)))) 400 uopSelIQMatrix.zipWithIndex.map{ case (u, i) => { 401 u.zipWithIndex.map{ case (uu, j) => { 402 uu := PopCount(uopSelIQ.take(i+1).map(x => x.zipWithIndex.filter(_._2 == j).map(_._1)).flatten) 403 }} 404 }} 405 val IQSelUop = Wire(Vec(IQEnqSum, ValidIO(new DynInst))) 406 val uopBlockByIQ = Wire(Vec(renameWidth, Bool())) 407 val allowDispatch = Wire(Vec(renameWidth, Bool())) 408 val thisCanActualOut = Wire(Vec(renameWidth, Bool())) 409 val lsqCanAccept = Wire(Bool()) 410 for (i <- 0 until RenameWidth){ 411 // update valid logic 412 fromRenameUpdate(i).valid := fromRename(i).valid && allowDispatch(i) && !uopBlockByIQ(i) && thisCanActualOut(i) && 413 lsqCanAccept && !fromRename(i).bits.eliminatedMove && !fromRename(i).bits.hasException && !fromRenameUpdate(i).bits.singleStep 414 fromRename(i).ready := allowDispatch(i) && !uopBlockByIQ(i) && thisCanActualOut(i) && lsqCanAccept 415 } 416 for (i <- 0 until RenameWidth){ 417 // check is drop amocas sta 418 fromRenameUpdate(i).bits.isDropAmocasSta := fromRename(i).bits.isAMOCAS && fromRename(i).bits.uopIdx(0) === 1.U 419 // update singleStep 420 fromRenameUpdate(i).bits.singleStep := io.singleStep && (fromRename(i).bits.robIdx =/= robidxCanCommitStepping) 421 } 422 var temp = 0 423 allIssueParams.zipWithIndex.map{ case(issue, iqidx) => { 424 for (i <- 0 until issue.numEnq){ 425 val oh = Wire(Vec(renameWidth, Bool())).suggestName(s"oh_IQSelUop_$temp") 426 oh := uopSelIQMatrix.map(_(iqidx)).map(_ === (i+1).U) 427 IQSelUop(temp) := PriorityMux(oh, fromRenameUpdate) 428 // there only assign valid not use PriorityMuxDefalut for better timing 429 IQSelUop(temp).valid := PriorityMuxDefault(oh.zip(fromRenameUpdate.map(_.valid)), false.B) 430 val allFuThisIQ = issue.exuBlockParams.map(_.fuConfigs).flatten.toSet.toSeq 431 val hasStaFu = !allFuThisIQ.filter(_.name == "sta").isEmpty 432 for (j <- 0 until numRegSrc){ 433 val maskForStd = hasStaFu && (j == 1) 434 val thisSrcHasInt = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) IntRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 435 val thisSrcHasFp = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) FpRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 436 val thisSrcHasVec = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) VecRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 437 val thisSrcHasV0 = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) V0RegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 438 val thisSrcHasVl = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) VlRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 439 val selSrcState = Seq(thisSrcHasInt || maskForStd, thisSrcHasFp || maskForStd, thisSrcHasVec, thisSrcHasV0, thisSrcHasVl) 440 IQSelUop(temp).bits.srcState(j) := PriorityMux(oh, allSrcState)(j).zip(selSrcState).filter(_._2 == true).map(_._1).foldLeft(false.B)(_ || _).asUInt 441 } 442 temp = temp + 1 443 if (backendParams.debugEn){ 444 dontTouch(oh) 445 } 446 } 447 }} 448 temp = 0 449 val uopBlockMatrix = Wire(Vec(renameWidth, Vec(issueQueueNum, Bool()))) 450 val uopBlockMatrixForAssign = allIssueParams.zipWithIndex.map { case (issue, iqidx) => { 451 val result = uopSelIQMatrix.map(_(iqidx)).map(x => Mux(io.toIssueQueues(temp).ready, x > issue.numEnq.U, x.orR)) 452 temp = temp + issue.numEnq 453 result 454 }}.transpose 455 uopBlockMatrix.zip(uopBlockMatrixForAssign).map(x => x._1 := VecInit(x._2)) 456 uopBlockByIQ := uopBlockMatrix.map(_.reduce(_ || _)) 457 io.toIssueQueues.zip(IQSelUop).map(x => { 458 x._1.valid := x._2.valid 459 x._1.bits := x._2.bits 460 }) 461 if (backendParams.debugEn){ 462 dontTouch(uopSelIQMatrix) 463 dontTouch(IQSelUop) 464 dontTouch(fromRenameUpdate) 465 dontTouch(uopBlockByIQ) 466 dontTouch(allowDispatch) 467 dontTouch(thisCanActualOut) 468 dontTouch(popFuTypeOH) 469 dontTouch(fuTypeOH) 470 dontTouch(fuTypeOHSingle) 471 dontTouch(minIQSelAll) 472 } 473 /////////////////////////////////////////////////////////// 474 475 val lsqEnqCtrl = Module(new LsqEnqCtrl) 476 477 // TODO: check lsqEnqCtrl redirect logic 478 // here is RegNext because dispatch2iq use s2_s4_redirect, newDispatch use s1_s3_redirect 479 lsqEnqCtrl.io.redirect := RegNext(io.redirect) 480 lsqEnqCtrl.io.lcommit := io.fromMem.lcommit 481 lsqEnqCtrl.io.scommit := io.fromMem.scommit 482 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.lqCancelCnt 483 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.sqCancelCnt 484 lsqEnqCtrl.io.enq.iqAccept := io.fromRename.map(x => !x.valid || x.fire) 485 io.toMem.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 486 487 private val enqLsqIO = lsqEnqCtrl.io.enq 488 private val lqFreeCount = lsqEnqCtrl.io.lqFreeCount 489 private val sqFreeCount = lsqEnqCtrl.io.sqFreeCount 490 491 private val numLoadDeq = LSQLdEnqWidth 492 private val numStoreAMODeq = LSQStEnqWidth 493 private val numVLoadDeq = LoadPipelineWidth 494 private val numDeq = enqLsqIO.req.size 495 lsqCanAccept := enqLsqIO.canAccept 496 497 private val isLoadVec = VecInit(fromRename.map(x => x.valid && FuType.isLoad(x.bits.fuType))) 498 private val isStoreVec = VecInit(fromRename.map(x => x.valid && FuType.isStore(x.bits.fuType))) 499 private val isAMOVec = fromRename.map(x => x.valid && FuType.isAMO(x.bits.fuType)) 500 private val isStoreAMOVec = fromRename.map(x => x.valid && (FuType.isStore(x.bits.fuType) || FuType.isAMO(x.bits.fuType))) 501 private val isVLoadVec = VecInit(fromRename.map(x => x.valid && FuType.isVLoad(x.bits.fuType))) 502 private val isVStoreVec = VecInit(fromRename.map(x => x.valid && FuType.isVStore(x.bits.fuType))) 503 504 private val loadCntVec = VecInit(isLoadVec.indices.map(x => PopCount(isLoadVec.slice(0, x + 1)))) 505 private val storeAMOCntVec = VecInit(isStoreAMOVec.indices.map(x => PopCount(isStoreAMOVec.slice(0, x + 1)))) 506 private val vloadCntVec = VecInit(isVLoadVec.indices.map(x => PopCount(isVLoadVec.slice(0, x + 1)))) 507 508 private val s0_enqLsq_resp = Wire(enqLsqIO.resp.cloneType) 509 for (i <- 0 until RenameWidth) { 510 // update lqIdx sqIdx 511 fromRenameUpdate(i).bits.lqIdx := s0_enqLsq_resp(i).lqIdx 512 fromRenameUpdate(i).bits.sqIdx := s0_enqLsq_resp(i).sqIdx 513 } 514 515 val loadBlockVec = VecInit(loadCntVec.map(_ > numLoadDeq.U)) 516 val storeAMOBlockVec = VecInit(storeAMOCntVec.map(_ > numStoreAMODeq.U)) 517 val vloadBlockVec = VecInit(vloadCntVec.map(_ > numVLoadDeq.U)) 518 val lsStructBlockVec = VecInit((loadBlockVec.zip(storeAMOBlockVec)).zip(vloadBlockVec).map(x => x._1._1 || x._1._2 || x._2)) 519 if (backendParams.debugEn) { 520 dontTouch(loadBlockVec) 521 dontTouch(storeAMOBlockVec) 522 dontTouch(lsStructBlockVec) 523 dontTouch(vloadBlockVec) 524 dontTouch(isLoadVec) 525 dontTouch(isVLoadVec) 526 dontTouch(loadCntVec) 527 } 528 529 private val uop = fromRename.map(_.bits) 530 private val fuType = uop.map(_.fuType) 531 private val fuOpType = uop.map(_.fuOpType) 532 private val vtype = uop.map(_.vpu.vtype) 533 private val sew = vtype.map(_.vsew) 534 private val lmul = vtype.map(_.vlmul) 535 private val eew = uop.map(_.vpu.veew) 536 private val mop = fuOpType.map(fuOpTypeItem => LSUOpType.getVecLSMop(fuOpTypeItem)) 537 private val nf = fuOpType.zip(uop.map(_.vpu.nf)).map { case (fuOpTypeItem, nfItem) => Mux(LSUOpType.isWhole(fuOpTypeItem), 0.U, nfItem) } 538 private val emul = fuOpType.zipWithIndex.map { case (fuOpTypeItem, index) => 539 Mux( 540 LSUOpType.isWhole(fuOpTypeItem), 541 GenUSWholeEmul(nf(index)), 542 Mux( 543 LSUOpType.isMasked(fuOpTypeItem), 544 0.U(mulBits.W), 545 EewLog2(eew(index)) - sew(index) + lmul(index) 546 ) 547 ) 548 } 549 550 private val isVlsType = fuType.map(fuTypeItem => FuType.isVls(fuTypeItem)).zip(fromRename.map(_.valid)).map(x => x._1 && x._2) 551 private val isLSType = fuType.map(fuTypeItem => FuType.isLoad(fuTypeItem) || FuType.isStore(fuTypeItem)).zip(fromRename.map(_.valid)).map(x => x._1 && x._2) 552 private val isSegment = fuType.map(fuTypeItem => FuType.isVsegls(fuTypeItem)).zip(fromRename.map(_.valid)).map(x => x._1 && x._2) 553 // TODO 554 private val isUnitStride = fuOpType.map(fuOpTypeItem => LSUOpType.isAllUS(fuOpTypeItem)) 555 private val isVecUnitType = isVlsType.zip(isUnitStride).map { case (isVlsTypeItme, isUnitStrideItem) => 556 isVlsTypeItme && isUnitStrideItem 557 } 558 private val isfofFixVlUop = uop.map { x => x.vpu.isVleff && x.lastUop } 559 private val instType = isSegment.zip(mop).map { case (isSegementItem, mopItem) => Cat(isSegementItem, mopItem) } 560 // There is no way to calculate the 'flow' for 'unit-stride' exactly: 561 // Whether 'unit-stride' needs to be split can only be known after obtaining the address. 562 // For scalar instructions, this is not handled here, and different assignments are done later according to the situation. 563 private val numLsElem = VecInit(uop.map(_.numLsElem)) 564 565 // The maximum 'numLsElem' number that can be emitted per port is: 566 // 16 2 2 2 2 2. 567 // The 'allowDispatch' calculations are done conservatively for timing purposes: 568 // The Flow of scalar instructions is considered 1, 569 // The flow of vector 'unit-stride' instructions is considered 2, and the flow of other vector instructions is considered 16. 570 private val conserveFlows = VecInit(isVlsType.zip(isLSType).zipWithIndex.map { case ((isVlsTyepItem, isLSTypeItem), index) => 571 Mux( 572 isVlsTyepItem, 573 Mux(isUnitStride(index), VecMemUnitStrideMaxFlowNum.U, 16.U), 574 Mux(isLSTypeItem, 1.U, 0.U) 575 ) 576 }) 577 578 // A conservative allocation strategy is adopted here. 579 // Vector 'unit-stride' instructions and scalar instructions can be issued from all six ports, 580 // while other vector instructions can only be issued from the first port 581 // if is segment instruction, need disptch it to Vldst_RS0, so, except port 0, stall other. 582 // The allocation needs to meet a few conditions: 583 // 1) The lsq has enough entris. 584 // 2) The number of flows accumulated does not exceed VecMemDispatchMaxNumber. 585 // 3) Vector instructions other than 'unit-stride' can only be issued on the first port. 586 587 588 for (index <- allowDispatch.indices) { 589 val flowTotal = Wire(UInt(log2Up(VirtualLoadQueueMaxStoreQueueSize + 1).W)) 590 flowTotal := conserveFlows.take(index + 1).reduce(_ +& _) 591 val allowDispatchPrevious = if (index == 0) true.B else allowDispatch(index - 1) 592 val allowDispatchThisUop = true.B 593 when(isStoreVec(index) || isVStoreVec(index)) { 594 allowDispatch(index) := (sqFreeCount > flowTotal) && allowDispatchThisUop && allowDispatchPrevious 595 }.elsewhen(isLoadVec(index) || isVLoadVec(index)) { 596 allowDispatch(index) := (lqFreeCount > flowTotal) && allowDispatchThisUop && allowDispatchPrevious 597 }.elsewhen(isAMOVec(index)) { 598 allowDispatch(index) := allowDispatchPrevious 599 }.otherwise { 600 allowDispatch(index) := allowDispatchPrevious 601 } 602 } 603 604 605 // enqLsq io 606 require(enqLsqIO.req.size == enqLsqIO.resp.size) 607 for (i <- enqLsqIO.req.indices) { 608 when(!io.fromRename(i).fire) { 609 enqLsqIO.needAlloc(i) := 0.U 610 }.elsewhen(isStoreVec(i) || isVStoreVec(i)) { 611 enqLsqIO.needAlloc(i) := 2.U // store | vstore 612 }.elsewhen(isLoadVec(i) || isVLoadVec(i)){ 613 enqLsqIO.needAlloc(i) := 1.U // load | vload 614 }.otherwise { 615 enqLsqIO.needAlloc(i) := 0.U 616 } 617 enqLsqIO.req(i).valid := io.fromRename(i).fire && !isAMOVec(i) && !isSegment(i) && !isfofFixVlUop(i) 618 enqLsqIO.req(i).bits := io.fromRename(i).bits 619 620 // This is to make it easier to calculate in LSQ. 621 // Both scalar instructions and vector instructions with FLOW equal to 1 have a NUM value of 1.” 622 // But, the 'numLsElem' that is not a vector is set to 0 when passed to IQ 623 enqLsqIO.req(i).bits.numLsElem := Mux(isVlsType(i), numLsElem(i), 1.U) 624 s0_enqLsq_resp(i) := enqLsqIO.resp(i) 625 } 626 627 val isFp = VecInit(fromRename.map(req => FuType.isFArith(req.bits.fuType))) 628 val isVec = VecInit(fromRename.map(req => FuType.isVArith (req.bits.fuType) || 629 FuType.isVsetRvfWvf(req.bits.fuType))) 630 val isMem = VecInit(fromRename.map(req => FuType.isMem(req.bits.fuType) || 631 FuType.isVls (req.bits.fuType))) 632 val isLs = VecInit(fromRename.map(req => FuType.isLoadStore(req.bits.fuType))) 633 val isVls = VecInit(fromRename.map(req => FuType.isVls (req.bits.fuType))) 634 val isStore = VecInit(fromRename.map(req => FuType.isStore(req.bits.fuType))) 635 val isVStore = VecInit(fromRename.map(req => FuType.isVStore(req.bits.fuType))) 636 val isAMO = VecInit(fromRename.map(req => FuType.isAMO(req.bits.fuType))) 637 val isBlockBackward = VecInit(fromRename.map(x => x.valid && x.bits.blockBackward)) 638 val isWaitForward = VecInit(fromRename.map(x => x.valid && x.bits.waitForward)) 639 640 val updatedUop = Wire(Vec(RenameWidth, new DynInst)) 641 val checkpoint_id = RegInit(0.U(64.W)) 642 checkpoint_id := checkpoint_id + PopCount((0 until RenameWidth).map(i => 643 fromRename(i).fire 644 )) 645 646 647 for (i <- 0 until RenameWidth) { 648 649 updatedUop(i) := fromRename(i).bits 650 updatedUop(i).debugInfo.eliminatedMove := fromRename(i).bits.eliminatedMove 651 // For the LUI instruction: psrc(0) is from register file and should always be zero. 652 when (fromRename(i).bits.isLUI) { 653 updatedUop(i).psrc(0) := 0.U 654 } 655 //TODO: vec ls mdp 656 io.lfst.req(i).valid := fromRename(i).fire && updatedUop(i).storeSetHit 657 io.lfst.req(i).bits.isstore := isStore(i) 658 io.lfst.req(i).bits.ssid := updatedUop(i).ssid 659 io.lfst.req(i).bits.robIdx := updatedUop(i).robIdx // speculatively assigned in rename 660 661 // override load delay ctrl signal with store set result 662 if(StoreSetEnable) { 663 updatedUop(i).loadWaitBit := io.lfst.resp(i).bits.shouldWait 664 updatedUop(i).waitForRobIdx := io.lfst.resp(i).bits.robIdx 665 } else { 666 updatedUop(i).loadWaitBit := isLs(i) && !isStore(i) && fromRename(i).bits.loadWaitBit 667 } 668 // // update singleStep, singleStep exception only enable in next machine instruction. 669 updatedUop(i).singleStep := io.singleStep && (fromRename(i).bits.robIdx =/= robidxCanCommitStepping) 670 when (fromRename(i).fire) { 671 XSDebug(TriggerAction.isDmode(updatedUop(i).trigger) || updatedUop(i).exceptionVec(breakPoint), s"Debug Mode: inst ${i} has frontend trigger exception\n") 672 XSDebug(updatedUop(i).singleStep, s"Debug Mode: inst ${i} has single step exception\n") 673 } 674 if (env.EnableDifftest) { 675 // debug runahead hint 676 val debug_runahead_checkpoint_id = Wire(checkpoint_id.cloneType) 677 if(i == 0){ 678 debug_runahead_checkpoint_id := checkpoint_id 679 } else { 680 debug_runahead_checkpoint_id := checkpoint_id + PopCount((0 until i).map(i => 681 fromRename(i).fire 682 )) 683 } 684 } 685 } 686 687 // store set perf count 688 XSPerfAccumulate("waittable_load_wait", PopCount((0 until RenameWidth).map(i => 689 fromRename(i).fire && fromRename(i).bits.loadWaitBit && !isStore(i) && isLs(i) 690 ))) 691 XSPerfAccumulate("storeset_load_wait", PopCount((0 until RenameWidth).map(i => 692 fromRename(i).fire && updatedUop(i).loadWaitBit && !isStore(i) && isLs(i) 693 ))) 694 XSPerfAccumulate("storeset_load_strict_wait", PopCount((0 until RenameWidth).map(i => 695 fromRename(i).fire && updatedUop(i).loadWaitBit && updatedUop(i).loadWaitStrict && !isStore(i) && isLs(i) 696 ))) 697 XSPerfAccumulate("storeset_store_wait", PopCount((0 until RenameWidth).map(i => 698 fromRename(i).fire && updatedUop(i).loadWaitBit && isStore(i) 699 ))) 700 701 val allResourceReady = io.enqRob.canAccept 702 703 // Instructions should enter dispatch queues in order. 704 // blockedByWaitForward: this instruction is blocked by itself (based on waitForward) 705 // nextCanOut: next instructions can out (based on blockBackward) 706 // notBlockedByPrevious: previous instructions can enqueue 707 val hasException = VecInit(fromRename.zip(updatedUop).map { 708 case (fromRename: DecoupledIO[DynInst], uop: DynInst) => 709 fromRename.bits.hasException || uop.singleStep 710 }) 711 712 private val blockedByWaitForward = Wire(Vec(RenameWidth, Bool())) 713 blockedByWaitForward(0) := !io.enqRob.isEmpty && isWaitForward(0) 714 for (i <- 1 until RenameWidth) { 715 blockedByWaitForward(i) := blockedByWaitForward(i - 1) || (!io.enqRob.isEmpty || Cat(fromRename.take(i).map(_.valid)).orR) && isWaitForward(i) 716 } 717 if(backendParams.debugEn){ 718 dontTouch(blockedByWaitForward) 719 dontTouch(conserveFlows) 720 } 721 722 // Only the uop with block backward flag will block the next uop 723 val nextCanOut = VecInit((0 until RenameWidth).map(i => 724 !isBlockBackward(i) 725 )) 726 val notBlockedByPrevious = VecInit((0 until RenameWidth).map(i => 727 if (i == 0) true.B 728 else Cat((0 until i).map(j => nextCanOut(j))).andR 729 )) 730 731 // for noSpecExec: (robEmpty || !this.noSpecExec) && !previous.noSpecExec 732 // For blockBackward: 733 // this instruction can actually dequeue: 3 conditions 734 // (1) resources are ready 735 // (2) previous instructions are ready 736 thisCanActualOut := VecInit((0 until RenameWidth).map(i => !blockedByWaitForward(i) && notBlockedByPrevious(i) && io.enqRob.canAccept)) 737 val thisActualOut = (0 until RenameWidth).map(i => io.enqRob.req(i).valid && io.enqRob.canAccept) 738 739 // input for ROB, LSQ 740 for (i <- 0 until RenameWidth) { 741 // needAlloc no use, need deleted 742 io.enqRob.needAlloc(i) := fromRename(i).valid 743 io.enqRob.req(i).valid := fromRename(i).fire 744 io.enqRob.req(i).bits := updatedUop(i) 745 io.enqRob.req(i).bits.hasException := updatedUop(i).hasException || updatedUop(i).singleStep 746 io.enqRob.req(i).bits.numWB := Mux(updatedUop(i).singleStep, 0.U, updatedUop(i).numWB) 747 } 748 749 val hasValidInstr = VecInit(fromRename.map(_.valid)).asUInt.orR 750 val hasSpecialInstr = Cat((0 until RenameWidth).map(i => isBlockBackward(i))).orR 751 752 private val canAccept = !hasValidInstr || !hasSpecialInstr && io.enqRob.canAccept 753 754 val isWaitForwardOrBlockBackward = isWaitForward.asUInt.orR || isBlockBackward.asUInt.orR 755 val renameFireCnt = PopCount(fromRename.map(_.fire)) 756 757 val stall_rob = hasValidInstr && !io.enqRob.canAccept 758 val stall_int_dq = hasValidInstr && io.enqRob.canAccept 759 val stall_int_dq0 = hasValidInstr && io.enqRob.canAccept 760 val stall_int_dq1 = hasValidInstr && io.enqRob.canAccept 761 val stall_fp_dq = hasValidInstr && io.enqRob.canAccept 762 val stall_ls_dq = hasValidInstr && io.enqRob.canAccept 763 764 XSPerfAccumulate("in_valid_count", PopCount(fromRename.map(_.valid))) 765 XSPerfAccumulate("in_fire_count", PopCount(fromRename.map(_.fire))) 766 XSPerfAccumulate("in_valid_not_ready_count", PopCount(fromRename.map(x => x.valid && !x.ready))) 767 XSPerfAccumulate("wait_cycle", !fromRename.head.valid && allResourceReady) 768 769 XSPerfAccumulate("stall_cycle_rob", stall_rob) 770 XSPerfAccumulate("stall_cycle_int_dq0", stall_int_dq0) 771 XSPerfAccumulate("stall_cycle_int_dq1", stall_int_dq1) 772 XSPerfAccumulate("stall_cycle_fp_dq", stall_fp_dq) 773 XSPerfAccumulate("stall_cycle_ls_dq", stall_ls_dq) 774 775 val notIssue = !io.debugTopDown.fromRob.robHeadLsIssue 776 val tlbReplay = io.debugTopDown.fromCore.fromMem.robHeadTlbReplay 777 val tlbMiss = io.debugTopDown.fromCore.fromMem.robHeadTlbMiss 778 val vioReplay = io.debugTopDown.fromCore.fromMem.robHeadLoadVio 779 val mshrReplay = io.debugTopDown.fromCore.fromMem.robHeadLoadMSHR 780 val l1Miss = io.debugTopDown.fromCore.fromMem.robHeadMissInDCache 781 val l2Miss = io.debugTopDown.fromCore.l2MissMatch 782 val l3Miss = io.debugTopDown.fromCore.l3MissMatch 783 784 val ldReason = Mux(l3Miss, TopDownCounters.LoadMemStall.id.U, 785 Mux(l2Miss, TopDownCounters.LoadL3Stall.id.U, 786 Mux(l1Miss, TopDownCounters.LoadL2Stall.id.U, 787 Mux(notIssue, TopDownCounters.MemNotReadyStall.id.U, 788 Mux(tlbMiss, TopDownCounters.LoadTLBStall.id.U, 789 Mux(tlbReplay, TopDownCounters.LoadTLBStall.id.U, 790 Mux(mshrReplay, TopDownCounters.LoadMSHRReplayStall.id.U, 791 Mux(vioReplay, TopDownCounters.LoadVioReplayStall.id.U, 792 TopDownCounters.LoadL1Stall.id.U)))))))) 793 794 val decodeReason = RegNextN(io.stallReason.reason, 2) 795 val renameReason = RegNext(io.stallReason.reason) 796 797 val stallReason = Wire(chiselTypeOf(io.stallReason.reason)) 798 val firedVec = fromRename.map(_.fire) 799 io.stallReason.backReason.valid := !canAccept 800 io.stallReason.backReason.bits := TopDownCounters.OtherCoreStall.id.U 801 stallReason.zip(io.stallReason.reason).zip(firedVec).zipWithIndex.map { case (((update, in), fire), idx) => 802 val headIsInt = FuType.isInt(io.robHead.getDebugFuType) && io.robHeadNotReady 803 val headIsFp = FuType.isFArith(io.robHead.getDebugFuType) && io.robHeadNotReady 804 val headIsDiv = FuType.isDivSqrt(io.robHead.getDebugFuType) && io.robHeadNotReady 805 val headIsLd = io.robHead.getDebugFuType === FuType.ldu.U && io.robHeadNotReady || !io.lqCanAccept 806 val headIsSt = io.robHead.getDebugFuType === FuType.stu.U && io.robHeadNotReady || !io.sqCanAccept 807 val headIsAmo = io.robHead.getDebugFuType === FuType.mou.U && io.robHeadNotReady 808 val headIsLs = headIsLd || headIsSt 809 val robLsFull = io.robFull || !io.lqCanAccept || !io.sqCanAccept 810 811 import TopDownCounters._ 812 update := MuxCase(OtherCoreStall.id.U, Seq( 813 // fire 814 (fire ) -> NoStall.id.U , 815 // dispatch not stall / core stall from decode or rename 816 (in =/= OtherCoreStall.id.U && in =/= NoStall.id.U ) -> in , 817 // rob stall 818 (headIsAmo ) -> AtomicStall.id.U , 819 (headIsSt ) -> StoreStall.id.U , 820 (headIsLd ) -> ldReason , 821 (headIsDiv ) -> DivStall.id.U , 822 (headIsInt ) -> IntNotReadyStall.id.U , 823 (headIsFp ) -> FPNotReadyStall.id.U , 824 (renameReason(idx) =/= NoStall.id.U ) -> renameReason(idx) , 825 (decodeReason(idx) =/= NoStall.id.U ) -> decodeReason(idx) , 826 )) 827 } 828 829 TopDownCounters.values.foreach(ctr => XSPerfAccumulate(ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)))) 830 831 val robTrueCommit = io.debugTopDown.fromRob.robTrueCommit 832 TopDownCounters.values.foreach(ctr => XSPerfRolling("td_"+ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)), 833 robTrueCommit, 1000, clock, reset)) 834 835 XSPerfHistogram("slots_fire", PopCount(thisActualOut), true.B, 0, RenameWidth+1, 1) 836 // Explaination: when out(0) not fire, PopCount(valid) is not meaningfull 837 XSPerfHistogram("slots_valid_pure", PopCount(io.enqRob.req.map(_.valid)), thisActualOut(0), 0, RenameWidth+1, 1) 838 XSPerfHistogram("slots_valid_rough", PopCount(io.enqRob.req.map(_.valid)), true.B, 0, RenameWidth+1, 1) 839 840 val perfEvents = Seq( 841 ("dispatch_in", PopCount(fromRename.map(_.valid && fromRename(0).ready)) ), 842 ("dispatch_empty", !hasValidInstr ), 843 ("dispatch_utili", PopCount(fromRename.map(_.valid)) ), 844 ("dispatch_waitinstr", PopCount(fromRename.map(!_.valid && canAccept)) ), 845 ("dispatch_stall_cycle_lsq", false.B ), 846 ("dispatch_stall_cycle_rob", stall_rob ), 847 ("dispatch_stall_cycle_int_dq", stall_int_dq ), 848 ("dispatch_stall_cycle_fp_dq", stall_fp_dq ), 849 ("dispatch_stall_cycle_ls_dq", stall_ls_dq ) 850 ) 851 generatePerfEvent() 852} 853