1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend.decode 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.rocket.DecodeLogic 22import xiangshan.backend.decode.Instructions._ 23import xiangshan.{FPUCtrlSignals, XSModule} 24 25class FPDecoder(implicit p: Parameters) extends XSModule{ 26 val io = IO(new Bundle() { 27 val instr = Input(UInt(32.W)) 28 val fpCtrl = Output(new FPUCtrlSignals) 29 }) 30 31 def X = BitPat("b?") 32 def N = BitPat("b0") 33 def Y = BitPat("b1") 34 val s = BitPat(S) 35 val d = BitPat(D) 36 val i = BitPat(I) 37 38 val default = List(X,X,X,N,N,N,X,X,X) 39 40 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 41 val single: Array[(BitPat, List[BitPat])] = Array( 42 FMV_W_X -> List(N,s,d,Y,N,Y,N,N,N), 43 FCVT_S_W -> List(N,s,s,Y,Y,Y,N,N,Y), 44 FCVT_S_WU-> List(N,s,s,Y,Y,Y,N,N,Y), 45 FCVT_S_L -> List(N,s,s,Y,Y,Y,N,N,Y), 46 FCVT_S_LU-> List(N,s,s,Y,Y,Y,N,N,Y), 47 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), 48 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 49 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 50 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 51 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 52 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 53 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 54 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 55 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 56 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 57 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 58 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 59 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 60 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 61 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 62 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 63 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 64 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 65 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 66 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 67 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 68 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 69 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 70 ) 71 72 73 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 74 val double: Array[(BitPat, List[BitPat])] = Array( 75 FMV_D_X -> List(N,d,d,Y,N,Y,N,N,N), 76 FCVT_D_W -> List(N,d,d,Y,Y,Y,N,N,Y), 77 FCVT_D_WU-> List(N,d,d,Y,Y,Y,N,N,Y), 78 FCVT_D_L -> List(N,d,d,Y,Y,Y,N,N,Y), 79 FCVT_D_LU-> List(N,d,d,Y,Y,Y,N,N,Y), 80 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 81 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 82 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 83 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 84 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 85 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 86 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 87 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 88 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 89 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 90 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 91 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 92 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 93 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 94 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 95 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 96 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 97 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 98 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 99 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 100 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 101 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 102 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 103 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 104 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 105 ) 106 107 val table = single ++ double 108 109 val decoder = DecodeLogic(io.instr, default, table) 110 111 val ctrl = io.fpCtrl 112 val sigs = Seq( 113 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 114 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 115 ctrl.div, ctrl.sqrt, ctrl.fcvt 116 ) 117 sigs.zip(decoder).foreach({case (s, d) => s := d}) 118 ctrl.typ := io.instr(21, 20) 119 ctrl.fmt := io.instr(26, 25) 120 ctrl.rm := io.instr(14, 12) 121 122 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 123 FADD_S -> List(BitPat("b00"),N), 124 FADD_D -> List(BitPat("b00"),N), 125 FSUB_S -> List(BitPat("b01"),N), 126 FSUB_D -> List(BitPat("b01"),N), 127 FMUL_S -> List(BitPat("b00"),N), 128 FMUL_D -> List(BitPat("b00"),N), 129 FMADD_S -> List(BitPat("b00"),Y), 130 FMADD_D -> List(BitPat("b00"),Y), 131 FMSUB_S -> List(BitPat("b01"),Y), 132 FMSUB_D -> List(BitPat("b01"),Y), 133 FNMADD_S-> List(BitPat("b11"),Y), 134 FNMADD_D-> List(BitPat("b11"),Y), 135 FNMSUB_S-> List(BitPat("b10"),Y), 136 FNMSUB_D-> List(BitPat("b10"),Y) 137 ) 138 val fmaDefault = List(BitPat("b??"), N) 139 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 140 DecodeLogic(io.instr, fmaDefault, fmaTable) 141 ).foreach({ 142 case (s, d) => s := d 143 }) 144} 145