1package xiangshan.backend.decode 2 3import chisel3._ 4import chisel3.util._ 5import freechips.rocketchip.rocket.DecodeLogic 6import xiangshan.backend.decode.Instructions._ 7import xiangshan.{FPUCtrlSignals, XSModule} 8 9class FPDecoder extends XSModule{ 10 val io = IO(new Bundle() { 11 val instr = Input(UInt(32.W)) 12 val fpCtrl = Output(new FPUCtrlSignals) 13 }) 14 15 def X = BitPat("b?") 16 def N = BitPat("b0") 17 def Y = BitPat("b1") 18 val s = BitPat(S) 19 val d = BitPat(D) 20 21 val default = List(X,X,X,N,N,N,X,X,X) 22 23 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 24 val single: Array[(BitPat, List[BitPat])] = Array( 25 FMV_W_X -> List(N,s,d,Y,N,Y,N,N,N), 26 FCVT_S_W -> List(N,s,s,Y,Y,Y,N,N,Y), 27 FCVT_S_WU-> List(N,s,s,Y,Y,Y,N,N,Y), 28 FCVT_S_L -> List(N,s,s,Y,Y,Y,N,N,Y), 29 FCVT_S_LU-> List(N,s,s,Y,Y,Y,N,N,Y), 30 FMV_X_W -> List(N,s,X,N,N,N,N,N,N), 31 FCLASS_S -> List(N,s,X,N,N,N,N,N,N), 32 FCVT_W_S -> List(N,s,X,N,Y,N,N,N,Y), 33 FCVT_WU_S-> List(N,s,X,N,Y,N,N,N,Y), 34 FCVT_L_S -> List(N,s,X,N,Y,N,N,N,Y), 35 FCVT_LU_S-> List(N,s,X,N,Y,N,N,N,Y), 36 FEQ_S -> List(N,s,X,N,Y,N,N,N,N), 37 FLT_S -> List(N,s,X,N,Y,N,N,N,N), 38 FLE_S -> List(N,s,X,N,Y,N,N,N,N), 39 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 40 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 41 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 42 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 43 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 44 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 45 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 46 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 47 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 48 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 49 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 50 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 51 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 52 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 53 ) 54 55 56 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 57 val double: Array[(BitPat, List[BitPat])] = Array( 58 FMV_D_X -> List(N,d,d,Y,N,Y,N,N,N), 59 FCVT_D_W -> List(N,d,d,Y,Y,Y,N,N,Y), 60 FCVT_D_WU-> List(N,d,d,Y,Y,Y,N,N,Y), 61 FCVT_D_L -> List(N,d,d,Y,Y,Y,N,N,Y), 62 FCVT_D_LU-> List(N,d,d,Y,Y,Y,N,N,Y), 63 FMV_X_D -> List(N,d,X,N,N,N,N,N,N), 64 FCLASS_D -> List(N,d,X,N,N,N,N,N,N), 65 FCVT_W_D -> List(N,d,X,N,Y,N,N,N,Y), 66 FCVT_WU_D-> List(N,d,X,N,Y,N,N,N,Y), 67 FCVT_L_D -> List(N,d,X,N,Y,N,N,N,Y), 68 FCVT_LU_D-> List(N,d,X,N,Y,N,N,N,Y), 69 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 70 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 71 FEQ_D -> List(N,d,X,N,Y,N,N,N,N), 72 FLT_D -> List(N,d,X,N,Y,N,N,N,N), 73 FLE_D -> List(N,d,X,N,Y,N,N,N,N), 74 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 75 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 76 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 77 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 78 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 79 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 80 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 81 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 82 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 83 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 84 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 85 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 86 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 87 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 88 ) 89 90 val table = single ++ double 91 92 val decoder = DecodeLogic(io.instr, default, table) 93 94 val ctrl = io.fpCtrl 95 val sigs = Seq( 96 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 97 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 98 ctrl.div, ctrl.sqrt, ctrl.fcvt 99 ) 100 sigs.zip(decoder).foreach({case (s, d) => s := d}) 101 ctrl.typ := io.instr(21,20) 102 ctrl.fmt := io.instr(26,25) 103 104 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 105 FADD_S -> List(BitPat("b00"),N), 106 FADD_D -> List(BitPat("b00"),N), 107 FSUB_S -> List(BitPat("b01"),N), 108 FSUB_D -> List(BitPat("b01"),N), 109 FMUL_S -> List(BitPat("b00"),N), 110 FMUL_D -> List(BitPat("b00"),N), 111 FMADD_S -> List(BitPat("b00"),Y), 112 FMADD_D -> List(BitPat("b00"),Y), 113 FMSUB_S -> List(BitPat("b01"),Y), 114 FMSUB_D -> List(BitPat("b01"),Y), 115 FNMADD_S-> List(BitPat("b11"),Y), 116 FNMADD_D-> List(BitPat("b11"),Y), 117 FNMSUB_S-> List(BitPat("b10"),Y), 118 FNMSUB_D-> List(BitPat("b10"),Y) 119 ) 120 val fmaDefault = List(BitPat("b??"), N) 121 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 122 DecodeLogic(io.instr, fmaDefault, fmaTable) 123 ).foreach({ 124 case (s, d) => s := d 125 }) 126} 127