1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils.{XSPerfAccumulate, XSPerfHistogram} 11import xiangshan._ 12import xiangshan.backend.BackendParams 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.issue.EntryBundles._ 19import xiangshan.backend.regfile._ 20import xiangshan.backend.PcToDataPathIO 21import xiangshan.backend.fu.FuType.is0latency 22 23class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 24 override def shouldBeInlined: Boolean = false 25 26 private implicit val dpParams: BackendParams = params 27 lazy val module = new DataPathImp(this) 28 29 println(s"[DataPath] Preg Params: ") 30 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 31 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 32} 33 34class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 35 extends LazyModuleImp(wrapper) with HasXSParameter { 36 37 val io = IO(new DataPathIO()) 38 39 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 40 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 41 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu) 42 43 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})") 44 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 45 46 // just refences for convience 47 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromVfIQ ++ fromMemIQ).toSeq 48 49 private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ 50 51 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toVfExu ++ toMemExu).toSeq 52 53 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 54 55 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 56 57 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 58 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 59 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 60 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 61 62 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 63 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 64 65 // port -> win 66 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 67 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 68 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 69 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 70 71 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 72 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 73 74 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid)).toSeq).toSeq 75 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid)).toSeq).toSeq 76 private val allDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq) 77 private val allNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq) 78 79 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 80 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 81 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 82 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 83 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 84 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 85 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 86// if (allNumRegSrcs(iqIdx)(exuIdx) == 2) { 87// val src0Req = inRFReadReqSeq(0).valid && allDataSources(iqIdx)(exuIdx)(0).readReg 88// val src1Req = inRFReadReqSeq(1).valid && allDataSources(iqIdx)(exuIdx)(1).readReg 89// if (srcIdx == 0) { 90// arbInSeq(srcIdx).valid := src0Req || src1Req 91// arbInSeq(srcIdx).bits.addr := Mux(src1Req && !src0Req, inRFReadReqSeq(1).bits.addr,inRFReadReqSeq(0).bits.addr) 92// } else { 93// arbInSeq(srcIdx).valid := src0Req && src1Req 94// arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 95// } 96// } else { 97// arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 98// arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 99// } 100 } else { 101 arbInSeq(srcIdx).valid := false.B 102 arbInSeq(srcIdx).bits.addr := 0.U 103 } 104 } 105 } 106 } 107 108 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 109 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 110 val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 111 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 112 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 113 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 114 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 115 } else { 116 arbInSeq(srcIdx).valid := false.B 117 arbInSeq(srcIdx).bits.addr := 0.U 118 } 119 } 120 } 121 } 122 123 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 124 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B)).toSeq).toSeq 125 126 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 127 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 128 arbIn.valid := inRFWriteReq 129 } 130 } 131 132 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 133 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 134 arbIn.valid := inRFWriteReq 135 } 136 } 137 138 private val intSchdParams = params.schdParams(IntScheduler()) 139 private val vfSchdParams = params.schdParams(VfScheduler()) 140 private val memSchdParams = params.schdParams(MemScheduler()) 141 142 private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu 143 private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu 144 // Todo: limit read port 145 private val numIntR = numIntRfReadByExu 146 private val numVfR = numVfRfReadByExu 147 println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})") 148 println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})") 149 150 private val schdParams = params.allSchdParams 151 152 private val pcReadValid = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathValid)) 153 private val pcReadFtqPtr = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqPtr)) 154 private val pcReadFtqOffset = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqOffset)) 155 private val targetPCRdata = io.fromPcTargetMem.toDataPathTargetPC 156 private val pcRdata = io.fromPcTargetMem.toDataPathPC 157 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 158 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 159 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 160 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 161 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 162 163 private val vfRfSplitNum = VLEN / XLEN 164 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 165 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 166 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 167 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 168 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 169 170 val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc) 171 assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}") 172 pcReadValid.zip(pcReadFtqPtrFormIQ.map(_.valid)).map(x => x._1 := x._2) 173 pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2) 174 pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2) 175 io.fromPcTargetMem.fromDataPathValid := pcReadValid 176 io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr 177 io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset 178 179 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 180 if (env.AlwaysBasicDiff || env.EnableDifftest) { 181 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 182 } else { None } 183 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 184 if (env.AlwaysBasicDiff || env.EnableDifftest) { 185 Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W)))) 186 } else { None } 187 188 private val fpDebugReadData: Option[Vec[UInt]] = 189 if (env.AlwaysBasicDiff || env.EnableDifftest) { 190 Some(Wire(Vec(32, UInt(XLEN.W)))) 191 } else { None } 192 private val vecDebugReadData: Option[Vec[UInt]] = 193 if (env.AlwaysBasicDiff || env.EnableDifftest) { 194 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 195 } else { None } 196 private val vconfigDebugReadData: Option[UInt] = 197 if (env.AlwaysBasicDiff || env.EnableDifftest) { 198 Some(Wire(UInt(64.W))) 199 } else { None } 200 201 202 fpDebugReadData.foreach(_ := vfDebugRead 203 .get._2 204 .slice(0, 32) 205 .map(_(63, 0)) 206 ) // fp only used [63, 0] 207 vecDebugReadData.foreach(_ := vfDebugRead 208 .get._2 209 .slice(32, 64) 210 .map(x => Seq(x(63, 0), x(127, 64))).flatten 211 ) 212 vconfigDebugReadData.foreach(_ := vfDebugRead 213 .get._2(64)(63, 0) 214 ) 215 216 io.debugVconfig.foreach(_ := vconfigDebugReadData.get) 217 218 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 219 bankNum = 4, 220 debugReadAddr = intDebugRead.map(_._1), 221 debugReadData = intDebugRead.map(_._2)) 222 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 223 debugReadAddr = vfDebugRead.map(_._1), 224 debugReadData = vfDebugRead.map(_._2)) 225 226 intRfWaddr := io.fromIntWb.map(_.addr).toSeq 227 intRfWdata := io.fromIntWb.map(_.data).toSeq 228 intRfWen := io.fromIntWb.map(_.wen).toSeq 229 230 for (portIdx <- intRfRaddr.indices) { 231 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 232 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 233 else 234 intRfRaddr(portIdx) := 0.U 235 } 236 237 vfRfWaddr := io.fromVfWb.map(x => RegEnable(x.addr, x.wen)).toSeq 238 vfRfWdata := io.fromVfWb.map(x => RegEnable(x.data, x.wen)).toSeq 239 vfRfWen.foreach(_.zip(io.fromVfWb.map(x => RegNext(x.wen))).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 240 241 for (portIdx <- vfRfRaddr.indices) { 242 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 243 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 244 else 245 vfRfRaddr(portIdx) := 0.U 246 } 247 248 249 intDebugRead.foreach { case (addr, _) => 250 addr := io.debugIntRat.get 251 } 252 253 vfDebugRead.foreach { case (addr, _) => 254 addr := io.debugFpRat.get ++ io.debugVecRat.get :+ io.debugVconfigRat.get 255 } 256 println(s"[DataPath] " + 257 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 258 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 259 260 val s1_addrOHs = Reg(MixedVec( 261 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 262 )) 263 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 264 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 265 )) 266 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 267 val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq)) 268 s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) => 269 s1Vec.zip(s0Vec).map { case (s1, s0) => 270 s1.imm := Mux(s0.valid, s0.bits.common.imm, s1.imm) 271 s1.immType := Mux(s0.valid, s0.bits.immType, s1.immType) 272 } 273 } 274 io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) => 275 out := reg 276 } 277 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq)))) 278 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq))) 279 280 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 281 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 282 283 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 284 285 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 286 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 287 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 288 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 289 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten 290 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 291 iuRdata.zip(realIuCfg) 292 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 293 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 294 } 295 } 296 297 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 298 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 299 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 300 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 301 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten 302 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 303 iuRdata.zip(realIuCfg) 304 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 305 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 306 } 307 } 308 309 val og0_cancel_no_load = VecInit(og0FailedVec2.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1).toSeq) 310 val exuParamsNoLoad = fromIQ.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu) 311 val is_0latency = Wire(Vec(og0_cancel_no_load.size, Bool())) 312 is_0latency := exuParamsNoLoad.map(x => is0latency(x._1.bits.common.fuType)) 313 val og0_cancel_delay = RegNext(VecInit(og0_cancel_no_load.zip(is_0latency).map(x => x._1 && x._2))) 314 val isVfScheduler = VecInit(exuParamsNoLoad.map(x => x._2.schdType.isInstanceOf[VfScheduler].B)) 315 val og0_cancel_delay_for_mem = VecInit(og0_cancel_delay.zip(isVfScheduler).map(x => x._1 && !x._2)) 316 for (i <- fromIQ.indices) { 317 for (j <- fromIQ(i).indices) { 318 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 319 // refs 320 val s1_valid = s1_toExuValid(i)(j) 321 val s1_ready = s1_toExuReady(i)(j) 322 val s1_data = s1_toExuData(i)(j) 323 val s1_addrOH = s1_addrOHs(i)(j) 324 val s0 = fromIQ(i)(j) // s0 325 326 val srcNotBlock = Wire(Bool()) 327 srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip vfRdArbWinner(i)(j)).map { case (source, win) => 328 !source.readReg || win._1 && win._2 329 }.fold(true.B)(_ && _) 330// if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 331// val src0VfBlock = s0.bits.common.dataSources(0).readReg && !vfRdArbWinner(i)(j)(0) 332// val src1VfBlock = s0.bits.common.dataSources(1).readReg && !vfRdArbWinner(i)(j)(1) 333// val src1IntBlock = s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg && !intRdArbWinner(i)(j)(1) 334// val src0IntBlock = (s0.bits.common.dataSources(0).readReg || s0.bits.common.dataSources(1).readReg) && !intRdArbWinner(i)(j)(0) 335// srcNotBlock := !src0VfBlock && !src1VfBlock && !src1IntBlock && !src0IntBlock 336// } 337 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && vfWbNotBlock(i)(j) 338 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 339 val s1_cancel = og1FailedVec2(i)(j) 340 val s0_cancel = Wire(Bool()) 341 val og0_cancel_delay_need = if (s0.bits.exuParams.schdType.isInstanceOf[MemScheduler]) og0_cancel_delay_for_mem else og0_cancel_delay 342 if (s0.bits.exuParams.isIQWakeUpSink) { 343 val exuOHNoLoad = s0.bits.common.l1ExuOH.get.map(x => x.asTypeOf(Vec(x.getWidth, Bool())).zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1)) 344 s0_cancel := exuOHNoLoad.zip(s0.bits.common.dataSources).map{ 345 case (exuOH, dataSource) => (VecInit(exuOH).asUInt & og0_cancel_delay_need.asUInt).orR && dataSource.readForward 346 }.reduce(_ || _) && s0.valid 347 } else s0_cancel := false.B 348 val s0_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 349 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel) { 350 s1_valid := s0.valid 351 s1_data.fromIssueBundle(s0.bits) // no src data here 352// if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 353// s1_data.dataSources(1).value := Mux(!s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg, DataSource.anotherReg, s0.bits.common.dataSources(1).value) 354// } 355 s1_addrOH := s0.bits.addrOH 356 }.otherwise { 357 s1_valid := false.B 358 } 359 s0.ready := (s1_ready || !s1_valid) && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel 360 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 361 } 362 } 363 364 private val fromIQFire = fromIQ.map(_.map(_.fire)) 365 private val toExuFire = toExu.map(_.map(_.fire)) 366 toIQs.zipWithIndex.foreach { 367 case(toIQ, iqIdx) => 368 toIQ.zipWithIndex.foreach { 369 case (toIU, iuIdx) => 370 // IU: issue unit 371 val og0resp = toIU.og0resp 372 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 373 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 374 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 375 og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) 376 og0resp.bits.resp := RespType.block 377 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 378 379 val og1resp = toIU.og1resp 380 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 381 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 382 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 383 og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) 384 // respType: fuIdle ->IQ entry clear 385 // fuUncertain ->IQ entry no action 386 // fuBusy ->IQ entry issued set false, then re-issue 387 // Only hyu, lda and sta are fuUncertain at OG1 stage 388 og1resp.bits.resp := Mux(!og1FailedVec2(iqIdx)(iuIdx), 389 if (toIU.issueQueueParams match { case x => x.isMemAddrIQ && !x.isVecMemIQ || x.inVfSchd}) RespType.uncertain else RespType.success, 390 RespType.block 391 ) 392 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 393 } 394 } 395 396 io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt 397 io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt 398 399 io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) => 400 cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire 401 cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B) 402 cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B) 403 cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B) 404 cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest 405 } 406 407 if (backendParams.debugEn){ 408 dontTouch(og0_cancel_no_load) 409 dontTouch(is_0latency) 410 dontTouch(og0_cancel_delay) 411 dontTouch(isVfScheduler) 412 dontTouch(og0_cancel_delay_for_mem) 413 } 414 for (i <- toExu.indices) { 415 for (j <- toExu(i).indices) { 416 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 417 // refs 418 val sinkData = toExu(i)(j).bits 419 // assign 420 toExu(i)(j).valid := s1_toExuValid(i)(j) 421 s1_toExuReady(i)(j) := toExu(i)(j).ready 422 sinkData := s1_toExuData(i)(j) 423 // s1Reg --[Ctrl]--> exu(s1) ---------- end 424 425 // s1Reg --[Data]--> exu(s1) ---------- begin 426 // data source1: preg read data 427 for (k <- sinkData.src.indices) { 428 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 429 430 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 431 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 432 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 433 else None) :+ 434 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 435 Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 436 else None) 437 ).filter(_.nonEmpty).map(_.get) 438 if (readRfMap.nonEmpty) 439 sinkData.src(k) := Mux1H(readRfMap) 440 } 441 if (sinkData.params.hasJmpFu) { 442 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 443 sinkData.pc.get := pcRdata(index) 444 } 445 if (sinkData.params.needTarget) { 446 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 447 sinkData.predictInfo.get.target := targetPCRdata(index) 448 } 449 } 450 } 451 452 if (env.AlwaysBasicDiff || env.EnableDifftest) { 453 val delayedCnt = 2 454 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 455 difftestArchIntRegState.coreid := io.hartId 456 difftestArchIntRegState.value := intDebugRead.get._2 457 458 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 459 difftestArchFpRegState.coreid := io.hartId 460 difftestArchFpRegState.value := fpDebugReadData.get 461 462 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 463 difftestArchVecRegState.coreid := io.hartId 464 difftestArchVecRegState.value := vecDebugReadData.get 465 } 466 467 val int_regcache_size = 48 468 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 469 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 470 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 471 for (i <- intRfWen.indices) { 472 when (intRfWen(i)) { 473 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 474 } 475 } 476 477 val vf_regcache_size = 48 478 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 479 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 480 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 481 for (i <- vfRfWen.indices) { 482 when (vfRfWen.head(i)) { 483 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 484 } 485 } 486 487 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 488 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 489 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 490 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 491 492 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 493 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 494 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 495 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 496 497 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 498 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 499 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 500 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 501 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 502 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 503 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 504 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 505 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 506 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 507 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 508 509 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 510 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 511 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 512 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 513 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 514 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 515 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 516 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 517 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 518 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 519 520 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 521 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 522 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 523 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 524 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 525 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 526 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 527 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 528 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 529 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 530} 531 532class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 533 // params 534 private val intSchdParams = params.schdParams(IntScheduler()) 535 private val vfSchdParams = params.schdParams(VfScheduler()) 536 private val memSchdParams = params.schdParams(MemScheduler()) 537 // bundles 538 val hartId = Input(UInt(8.W)) 539 540 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 541 542 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 543 544 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 545 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 546 547 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 548 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 549 550 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 551 552 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 553 554 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 555 556 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 557 558 val og0CancelOH = Output(ExuOH(backendParams.numExu)) 559 560 val og1CancelOH = Output(ExuOH(backendParams.numExu)) 561 562 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 563 564 val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal)) 565 566 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 567 568 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 569 570 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 571 572 val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo)) 573 574 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 575 576 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 577 578 val fromPcTargetMem = Flipped(new PcToDataPathIO(params)) 579 580 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 581 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 582 val debugVecRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 583 val debugVconfigRat = if (params.debugEn) Some(Input(UInt(vfSchdParams.pregIdxWidth.W))) else None 584 val debugVconfig = if (params.debugEn) Some(Output(UInt(XLEN.W))) else None 585} 586