1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{Rename, BusyTable} 9import xiangshan.backend.brq.Brq 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN))) 20 // int block only uses port 0~7 21 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 22 val redirect = ValidIO(new Redirect) 23} 24 25class CtrlToFpBlockIO extends XSBundle { 26 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 27 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1))) 28 // fp block uses port 0~11 29 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 30 val redirect = ValidIO(new Redirect) 31} 32 33class CtrlToLsBlockIO extends XSBundle { 34 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 35 val enqLsq = Flipped(new LsqEnqIO) 36 val redirect = ValidIO(new Redirect) 37} 38 39class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 40 val io = IO(new Bundle { 41 val frontend = Flipped(new FrontendToBackendIO) 42 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 43 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 44 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 45 val toIntBlock = new CtrlToIntBlockIO 46 val toFpBlock = new CtrlToFpBlockIO 47 val toLsBlock = new CtrlToLsBlockIO 48 val roqio = new Bundle { 49 // to int block 50 val toCSR = new RoqCSRIO 51 val exception = ValidIO(new MicroOp) 52 val isInterrupt = Output(Bool()) 53 // to mem block 54 val commits = new RoqCommitIO 55 val roqDeqPtr = Output(new RoqPtr) 56 } 57 }) 58 59 val decode = Module(new DecodeStage) 60 val brq = Module(new Brq) 61 val rename = Module(new Rename) 62 val dispatch = Module(new Dispatch) 63 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 64 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 65 66 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 67 68 val roq = Module(new Roq(roqWbSize)) 69 70 // When replay and mis-prediction have the same roqIdx, 71 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 72 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 73 val brqIsAfterLsq = isAfter(brq.io.redirectOut.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 74 val redirectArb = Mux(io.fromLsBlock.replay.valid && (!brq.io.redirectOut.valid || brqIsAfterLsq), 75 io.fromLsBlock.replay.bits, brq.io.redirectOut.bits) 76 val redirectValid = roq.io.redirectOut.valid || brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 77 val redirect = Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits, redirectArb) 78 79 io.frontend.redirect.valid := RegNext(redirectValid) 80 io.frontend.redirect.bits := RegNext(Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits.target, redirectArb.target)) 81 io.frontend.cfiUpdateInfo <> brq.io.cfiInfo 82 83 decode.io.in <> io.frontend.cfVec 84 decode.io.enqBrq <> brq.io.enq 85 86 brq.io.redirect.valid <> redirectValid 87 brq.io.redirect.bits <> redirect 88 brq.io.bcommit <> roq.io.bcommit 89 brq.io.exuRedirectWb <> io.fromIntBlock.exuRedirect 90 91 // pipeline between decode and dispatch 92 val lastCycleRedirect = RegNext(redirectValid) 93 for (i <- 0 until RenameWidth) { 94 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, redirectValid || lastCycleRedirect) 95 } 96 97 rename.io.redirect.valid <> redirectValid 98 rename.io.redirect.bits <> redirect 99 rename.io.roqCommits <> roq.io.commits 100 rename.io.out <> dispatch.io.fromRename 101 rename.io.renameBypass <> dispatch.io.renameBypass 102 103 dispatch.io.redirect.valid <> redirectValid 104 dispatch.io.redirect.bits <> redirect 105 dispatch.io.enqRoq <> roq.io.enq 106 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 107 dispatch.io.readIntRf <> io.toIntBlock.readRf 108 dispatch.io.readFpRf <> io.toFpBlock.readRf 109 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 110 intBusyTable.io.allocPregs(i).valid := preg.isInt 111 fpBusyTable.io.allocPregs(i).valid := preg.isFp 112 intBusyTable.io.allocPregs(i).bits := preg.preg 113 fpBusyTable.io.allocPregs(i).bits := preg.preg 114 } 115 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 116 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 117// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 118 119 120 val flush = redirectValid && RedirectLevel.isUnconditional(redirect.level) 121 fpBusyTable.io.flush := flush 122 intBusyTable.io.flush := flush 123 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 124 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 125 setPhyRegRdy.bits := wb.bits.uop.pdest 126 } 127 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 128 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 129 setPhyRegRdy.bits := wb.bits.uop.pdest 130 } 131 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 132 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 133 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 134 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 135 136 roq.io.redirect.valid := brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 137 roq.io.redirect.bits <> redirectArb 138 roq.io.exeWbResults.take(roqWbSize-1).zip( 139 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 140 ).foreach{ 141 case(x, y) => 142 x.bits := y.bits 143 x.valid := y.valid && !y.bits.redirectValid 144 } 145 roq.io.exeWbResults.last := brq.io.out 146 147 io.toIntBlock.redirect.valid := redirectValid 148 io.toIntBlock.redirect.bits := redirect 149 io.toFpBlock.redirect.valid := redirectValid 150 io.toFpBlock.redirect.bits := redirect 151 io.toLsBlock.redirect.valid := redirectValid 152 io.toLsBlock.redirect.bits := redirect 153 154 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 155 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 156 157 // roq to int block 158 io.roqio.toCSR <> roq.io.csr 159 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 160 io.roqio.exception.bits := roq.io.exception 161 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 162 // roq to mem block 163 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 164 io.roqio.commits := roq.io.commits 165} 166