1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{Rename, BusyTable} 9import xiangshan.backend.brq.Brq 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 20 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 21 val redirect = ValidIO(new Redirect) 22} 23 24class CtrlToFpBlockIO extends XSBundle { 25 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 26 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 27 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 28 val redirect = ValidIO(new Redirect) 29} 30 31class CtrlToLsBlockIO extends XSBundle { 32 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 33 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 34 val enqLsq = Flipped(new LsqEnqIO) 35 val redirect = ValidIO(new Redirect) 36} 37 38class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 39 val io = IO(new Bundle { 40 val frontend = Flipped(new FrontendToBackendIO) 41 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 42 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 43 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 44 val toIntBlock = new CtrlToIntBlockIO 45 val toFpBlock = new CtrlToFpBlockIO 46 val toLsBlock = new CtrlToLsBlockIO 47 val roqio = new Bundle { 48 // to int block 49 val toCSR = new RoqCSRIO 50 val exception = ValidIO(new MicroOp) 51 val isInterrupt = Output(Bool()) 52 // to mem block 53 val commits = new RoqCommitIO 54 val roqDeqPtr = Output(new RoqPtr) 55 } 56 }) 57 58 val decode = Module(new DecodeStage) 59 val brq = Module(new Brq) 60 val rename = Module(new Rename) 61 val dispatch = Module(new Dispatch) 62 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 63 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 64 65 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 66 67 val roq = Module(new Roq(roqWbSize)) 68 69 // When replay and mis-prediction have the same roqIdx, 70 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 71 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 72 val brqIsAfterLsq = isAfter(brq.io.redirect.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 73 val redirectArb = Mux(io.fromLsBlock.replay.valid && (!brq.io.redirect.valid || brqIsAfterLsq), 74 io.fromLsBlock.replay.bits, brq.io.redirect.bits) 75 val redirectValid = roq.io.redirect.valid || brq.io.redirect.valid || io.fromLsBlock.replay.valid 76 val redirect = Mux(roq.io.redirect.valid, roq.io.redirect.bits, redirectArb) 77 78 io.frontend.redirect.valid := RegNext(redirectValid) 79 io.frontend.redirect.bits := RegNext(Mux(roq.io.redirect.valid, roq.io.redirect.bits.target, redirectArb.target)) 80 // io.frontend.cfiUpdateInfo <> brq.io.cfiInfo 81 io.frontend.cfiUpdateInfo <> brq.io.cfiInfo 82 83 decode.io.in <> io.frontend.cfVec 84 decode.io.toBrq <> brq.io.enqReqs 85 decode.io.brTags <> brq.io.brTags 86 87 brq.io.roqRedirect <> roq.io.redirect 88 brq.io.memRedirect.valid := brq.io.redirect.valid || io.fromLsBlock.replay.valid 89 brq.io.memRedirect.bits <> redirectArb 90 brq.io.bcommit <> roq.io.bcommit 91 brq.io.enqReqs <> decode.io.toBrq 92 brq.io.exuRedirect <> io.fromIntBlock.exuRedirect 93 94 // pipeline between decode and dispatch 95 val lastCycleRedirect = RegNext(redirectValid) 96 for (i <- 0 until RenameWidth) { 97 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, redirectValid || lastCycleRedirect) 98 } 99 100 rename.io.redirect.valid <> redirectValid 101 rename.io.redirect.bits <> redirect 102 rename.io.roqCommits <> roq.io.commits 103 rename.io.out <> dispatch.io.fromRename 104 rename.io.renameBypass <> dispatch.io.renameBypass 105 106 dispatch.io.redirect.valid <> redirectValid 107 dispatch.io.redirect.bits <> redirect 108 dispatch.io.enqRoq <> roq.io.enq 109 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 110 dispatch.io.readIntRf <> io.toIntBlock.readRf 111 dispatch.io.readFpRf <> io.toFpBlock.readRf 112 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 113 intBusyTable.io.allocPregs(i).valid := preg.isInt 114 fpBusyTable.io.allocPregs(i).valid := preg.isFp 115 intBusyTable.io.allocPregs(i).bits := preg.preg 116 fpBusyTable.io.allocPregs(i).bits := preg.preg 117 } 118 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 119 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 120 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 121 122 123 val flush = redirectValid && (redirect.isException || redirect.isFlushPipe) 124 fpBusyTable.io.flush := flush 125 intBusyTable.io.flush := flush 126 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 127 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U) 128 setPhyRegRdy.bits := wb.bits.uop.pdest 129 } 130 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 131 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 132 setPhyRegRdy.bits := wb.bits.uop.pdest 133 } 134 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 135 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 136 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 137 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 138 139 roq.io.memRedirect := DontCare 140 roq.io.memRedirect.valid := false.B 141 roq.io.brqRedirect.valid := brq.io.redirect.valid || io.fromLsBlock.replay.valid 142 roq.io.brqRedirect.bits <> redirectArb 143 roq.io.exeWbResults.take(roqWbSize-1).zip( 144 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 145 ).foreach{ 146 case(x, y) => 147 x.bits := y.bits 148 x.valid := y.valid && !y.bits.redirectValid 149 } 150 roq.io.exeWbResults.last := brq.io.out 151 152 io.toIntBlock.redirect.valid := redirectValid 153 io.toIntBlock.redirect.bits := redirect 154 io.toFpBlock.redirect.valid := redirectValid 155 io.toFpBlock.redirect.bits := redirect 156 io.toLsBlock.redirect.valid := redirectValid 157 io.toLsBlock.redirect.bits := redirect 158 159 // roq to int block 160 io.roqio.toCSR <> roq.io.csr 161 io.roqio.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 162 io.roqio.exception.bits := roq.io.exception 163 io.roqio.isInterrupt := roq.io.redirect.bits.isFlushPipe 164 // roq to mem block 165 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 166 io.roqio.commits := roq.io.commits 167} 168